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SRAM anti-sso output self-regulation circuit

A self-adjusting, circuit technology, applied in information storage, static memory, digital memory information, etc., can solve problems such as circuit failure, disadvantage, disadvantage, and timely avoid SSO, and achieve the effect of reducing high current and avoiding IRDrop.

Active Publication Date: 2020-10-09
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

One of the defects of this method is that the control signal is controlled by the outside, it is difficult to achieve precise control, which is not conducive to avoiding SSO in time; the second defect is that there is only one delayed output data interval, and if the delayed output data of this interval cannot solve the SSO problem If there is any impact, the circuit will also fail, which is not conducive to avoiding SSO in a targeted manner.

Method used

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  • SRAM anti-sso output self-regulation circuit

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Embodiment Construction

[0032] The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0033] In one embodiment of the present invention, it is to provide a SRAM anti-SSO output self-adjusting circuit to reduce the large current caused by multiple IOs flipping the output simultaneously, thereby avoiding IR Drop. Specifically, see figure 2 , figure 2 It is a schematic diagram of an output self-adjusting circuit for preventing SSO according to an embodiment of the present invention. Such as figure 2 As shown, the SRAM anti-SSO output self-regulating circuit provided in an embodiment of the prese...

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Abstract

The invention relates to an SRAM anti-SSO output self-adjusting circuit, which relates to the integrated circuit design field and comprises n output data sensing modules for detecting the output dataD [n-1, 0]is reversed with respect to the previous clock state; A flip counting module that receives the n data flip judgment signals D [i] _ sensor output from the n output data sensing modules and calculates the n data flip judgment signals D [i] _ sensor to obtain a corresponding sum signal and a carry signal; A logic encoding module that encodes the sum signal and the carry signal provided bythe flip counting module to provide a control signal S [i] of different delay grades, wherein z is an integer greater than or equal to 1; And a delay control module that controls different delay gearsthrough the control signal S [i] (0<=i<=z-1) provided by the logic encoding module so as to output the simultaneously flipped data sequence so as to automatically re-adjust the output timing of the simultaneously flipped output data.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an SRAM anti-SSO output self-adjusting circuit. Background technique [0002] In the field of integrated circuit design, Static Random-Access Memory (SRAM) is a common device. [0003] However, the current SRAM has the problem of multiple IOs flipping the output at the same time to cause a large current, which in turn causes a large resistance drop (IR Drop). At present, the anti-simultaneous flipping output (SSO) circuit commonly used in the industry can be found in figure 1 , figure 1 It is a schematic diagram of an anti-SSO circuit in the prior art. Such as figure 1 As shown, the delay control signal S in the prior art is controlled externally, and the switch controlled by S determines whether half of the output data is output with a delay. One of the defects of this method is that the control signal is controlled by the outside, it is difficult to achieve precise...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413G11C11/412
CPCG11C11/4125G11C11/413
Inventor 何宏瑾刘雯胡晓明
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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