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Method for forming three-dimensional memory and three-dimensional memory

A memory, three-dimensional technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problem of bridge contact between materials and through-array barrier structures, and achieve the effect of reducing size, reducing resistance value, and reasonable layout

Active Publication Date: 2020-06-23
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the distance between the grid line gap and the through-array barrier structure needs to be reduced, but this may cause the material in the grid line gap to bridge or even contact the through-array barrier structure.

Method used

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  • Method for forming three-dimensional memory and three-dimensional memory
  • Method for forming three-dimensional memory and three-dimensional memory
  • Method for forming three-dimensional memory and three-dimensional memory

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Embodiment Construction

[0026] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0027] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

[0028] As indicated in this application and claims, the terms "a", "an", "an" and / or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other st...

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Abstract

The invention relates to a method of forming a three-dimensional memory and a three-dimensional memory. The three-dimensional memory includes an array storage area having at least one block storage area. The block storage area includes: a substrate and stacked layers on the substrate, the stacked layers include alternately stacked gate layers and dielectric layers along a direction perpendicular to the substrate; first gate line gaps and second gate gaps arranged at intervals line gap; one or more third grid line gaps located between the first grid line gap and the second grid line gap; the penetrating array barrier structure located between adjacent grid line gaps; and the penetrating array barrier structure located along the A column of dummy channel structures on at least one side of the extending direction of the gate line gaps; wherein at least one of the one or more third gate line gaps is disconnected at a position corresponding to the column of dummy channel structures.

Description

technical field [0001] The present invention mainly relates to a semiconductor manufacturing method, and in particular to a method for forming a three-dimensional memory and a three-dimensional memory. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, the industry has developed memory devices having a three-dimensional (3D) structure, which improves integration density by three-dimensionally arranging memory cells over a substrate. [0003] In a three-dimensional memory device such as 3D NAND flash memory, the array storage area may include one or more block storage areas (blocks). The block storage area may further include a plurality of finger storage areas (fingers) separated by Gate Line Slits (GLS). A Through Array Barrier (TAB) and a Through Array Contact (TAC) located therein are provided in the finger storage area. With the increase of the storage density in the array storage area, the pitch of each pattern needs ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L27/1157H01L27/11575H01L27/11582H01L27/11524H01L27/11548H01L27/11556H10B69/00H10B41/27H10B41/35H10B41/50H10B43/27H10B43/35H10B43/50
CPCH10B41/50H10B41/35H10B43/50H10B41/27H10B43/35H10B69/00H10B43/27
Inventor 宋玉洁夏志良华文宇刘藩东
Owner YANGTZE MEMORY TECH CO LTD
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