Flash memory structure and corresponding programming, erasing and reading methods

Abstract

The invention relates to a flash memory structure, comprising: a substrate, a source region, a drain region and a channel region between the source region and the drain region are arranged in the substrate, and the substrate and the channel adopt P-type Impurity doping, the source region and the drain region are doped with high-concentration N-type impurities; and a tunnel oxide layer, a charge storage layer, a blocking oxide layer and a control gate layer are sequentially stacked on the base of the channel region. The present invention utilizes back gate bias to assist band tunneling hot hole injection for programming, hot holes can enter the charge storage layer under the condition of low voltage difference to realize programming, and the requirement for capacitive coupling coefficient is relatively low. The channel electron injection method is used for erasing, and the electrons in the channel can also enter the charge storage layer under the condition of low voltage difference, so that the holes and electrons are combined one by one, and the holes entering the charge storage layer are gradually erased during programming. holes, avoiding the problems of erasing saturation and process window reduction caused by the high-voltage FN erasing mechanism in the prior art.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a flash memory structure and corresponding programming, erasing and reading methods. Background technique [0002] In the prior art, the flash memory is usually programmed by using the BackBiasAssisted Band-to-Band Tunneling Induced Hot Electron Injection (B4-Flash) method , due to the introduction of the back gate bias to replace a part of the source-drain voltage, the voltage difference between the source and drain can be smaller than that of traditional flash memory, which is conducive to reducing the size of flash memory. The current B4-Flash flash memory structure is a p-type channel. [0003] The inventors found that, for the currently used p-type channel flash memory structure of B4-Flash, the electron tunneling effect of Fowler-Nordheim (FN) is usually used to erase the electrons in the charge storage layer. When erasing, it is necessary to apply a very large voltage diffe...

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Problems solved by technology

[0004] According to the analysis of background technology, p-channel B4-Flash cannot solve the problem of small process window caused by erasing saturation within its own device structure and process framework

Due to the small size of the device, the capacitive coupling coefficient between the B4-Flash control gate and the charge storage layer is naturally relatively small. To completely solve the problem of small process window caused by erase saturation, it must be replaced by a new erase method. The FN erasing method that requires a large voltage, the new erasing method should be that the voltage between the control gate and the substrate does not need to be very large

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