30 results about "Hot holes" patented technology

Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.

Programming a NVM memory cell such as an NROM cell by using hot hole injection (HHI), followed by channel hot electron (CHE) injection. CHE injection increases the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in HHI programming step. Page Write may be performed using a combination of only HHI, followed by CHE without any Erase.

Methods for removing, or leaching, cobalt or other diamond-diamond bonding catalysts from polycrystalline diamond compacts (PDCs) or other structures formed from polycrystalline diamond include leaching under conditions that simulate use of PDCs in a hot hole drilling environment. A leaching agent may be formulated, when used under appropriate conditions, to remove or substantially remove cobalt or another catalyst from polycrystalline diamond without dissolving, degrading or otherwise attacking a substrate that supports or carries the polycrystalline diamond. The leaching agent may include one or more components that mimick the chemicals or conditions to which a PDC would be exposed in a hot hole drilling environment. Polycrystalline diamond structures from which cobalt or another diamond-diamond bonding catalyst has been removed or substantially removed are also disclosed, as are systems for leaching cobalt or other diamond-diamond bonding catalysts from polycrystalline diamond.

An apparatus, method and insulation medium for inserting and insulating a charge medium within a borehole includes a charge tube comprised of an elongate tube having a length and diameter sufficient for containing a desired quantity of a charge medium. A charge medium in a pumpable form is provided for substantially filling the charge tube. An insulation medium in a pumpable form is provided for substantially encapsulating the charge tube and substantially filling an annular space between the charge tube and the borehole for insulating the charge tube from a downhole environment in which the charge tube is to be inserted. A detonator is inserted within the charge medium proximate a distal end of the charge tube and a charge cable extends from the detonator through the charge tube and exits from the charge tube.

The present invention provides a high-speed low-voltage programming scheme and self-convergent high-speed low-voltage erasing schemes for Electrically Erasable Programmable Read-Only Memories. For the N-type Field Effect Transistor based NVM programming, an elevated source voltage to the substrate can achieve high efficient Drain-Avalanche-Hot-Electron Injection into the floating gate resulting in high-speed and low-voltage operations. The self-convergent and low-voltage erasing can be achieved by applying Drain-Avalanche-Hot Hole Injection with the conditions of restricted maximum drain current and a moderate control gate voltage enough to turn on the NFET. For the p-type FET based EEPROM programming, a negative source voltage relative to the substrate can achieve high efficient Drain-Avalanche-Hot-Hole Injection into the floating gate resulting in high-speed and low voltage operations. The self-convergent and low voltage erasing can be achieved by applying Drain-Avalanche-Hot-Electron Injection with the conditions of restricted maximum magnitude of drain current and a negative moderate control gate voltage enough to turn on the PFET.

A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.

A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.

The invention discloses a hole ironing unit device which comprises a base. A bottom pit is formed in the base and communicated with an air pump. By changing a mode, forming is firstly implemented, drilling is secondly implemented, drilled holes are ironed in a coil heating manner, the device effectively solves the problems of deformation of the holes and edge layering of the holes, the holes of an interlayer of each mask are kept consistent, and waste of raw materials is reduced.

Methods for removing, or leaching, cobalt or other diamond-diamond bonding catalysts from polycrystalline diamond compacts (PDCs) or other structures formed from polycrystalline diamond include leaching under conditions that simulate use of PDCs in a hot hole drilling environment. A leaching agent may be formulated, when used under appropriate conditions, to remove or substantially remove cobalt or another catalyst from polycrystalline diamond without dissolving, degrading or otherwise attacking a substrate that supports or carries the polycrystalline diamond. The leaching agent may include one or more components that mimick the chemicals or conditions to which a PDC would be exposed in a hot hole drilling environment. Polycrystalline diamond structures from which cobalt or another diamond-diamond bonding catalyst has been removed or substantially removed are also disclosed, as are systems for leaching cobalt or other diamond-diamond bonding catalysts from polycrystalline diamond.

The invention provides a flash memory unit, a flash memory array and an operation method thereof, comprising: an N well is formed in a P-type substrate, a P-type doped region is formed in the N well, and the P-type doped region is used as the first A source, a second source, and a drain; the gate structure on the N well is located between the first source and the second source, and the gate structure has a symmetrical shape about the erasing gate Two storage bits, each containing a floating gate and a word line gate. The flash memory unit provided by the present invention is programmed by generating high-energy electrons or even hot electrons through the collision ionization of hot holes at the drain pinch-off point, which is beneficial to the miniaturization of the device and achieves the purpose of reducing the area of ​​the device unit, and the flash memory unit provided by the present invention With a special erasing gate, it can be erased without applying high voltage to the word line gate, so that the second oxide layer under the word line gate can be made very thin, so the read voltage can be very small, which simplifies the design of the read circuit .

The invention relates to a device for reaming needles for lithium battery cells, which is characterized in that it includes a cell clamping and moving mechanism, a scalding needle transmission mechanism, and a scalding needle heating mechanism; the cell clamping and moving mechanism includes a The cell gripper, the guide gripper of the cell, and the cell moving mechanism that drives the cell gripper and the guide gripper to move to the reaming station, and the guide gripper is provided with a guide hole coaxial with the cell; The needle ironing transmission mechanism includes a driving sprocket, a driven sprocket and a chain wound between the driving sprocket and the driven sprocket, and a plurality of ironing installation plates are fixed on the chain, and the ironing installation plates are installed Go to the needle ironing seat with heat insulation effect, and install the ironing needle on the needle ironing seat. The invention can accurately and quickly complete the ironing hole in the center of the circular battery core, and can avoid damage to the transmission chain caused by the high temperature of the ironing needle.

The invention belongs to a integrated circuit reliability test technology field and especially relates to a multifunctional test circuit of integrated circuit stress degradation and a test method thereof. A core part of the test circuit takes an annular oscillator as a basis. Several auxiliary transistors, switch transistors and control terminals are added. By using the circuit and the method of the invention, a negative bias temperature instability, a positive bias temperature instability, hot hole injection or hot electron injection stress can be applied to pMOSFETs or nMOSFETs in a ring vibration inverter respectively; a ring oscillator is in a normal oscillation and stress oscillation state; the pMOSFETs or nMOSFETs of the inverter in the ring oscillator is in a measuring state of a charge pump. The degradation of the MOSFETs in the ring vibration inverter can be shown through changes of a ring oscillator oscillation frequency after the stress and can be shown through the changes of a CP current (Icpp or Icpn) of the pMOSFETs or nMOSFETs in the ring oscillator.

The invention relates to a flash memory structure, comprising: a substrate, a source region, a drain region and a channel region between the source region and the drain region are arranged in the substrate, and the substrate and the channel adopt P-type Impurity doping, the source region and the drain region are doped with high-concentration N-type impurities; and a tunnel oxide layer, a charge storage layer, a blocking oxide layer and a control gate layer are sequentially stacked on the base of the channel region. The present invention utilizes back gate bias to assist band tunneling hot hole injection for programming, hot holes can enter the charge storage layer under the condition of low voltage difference to realize programming, and the requirement for capacitive coupling coefficient is relatively low. The channel electron injection method is used for erasing, and the electrons in the channel can also enter the charge storage layer under the condition of low voltage difference, so that the holes and electrons are combined one by one, and the holes entering the charge storage layer are gradually erased during programming. holes, avoiding the problems of erasing saturation and process window reduction caused by the high-voltage FN erasing mechanism in the prior art.

The invention provides a flash memory unit, a flash memory array and an operation method thereof, comprising: an N well is formed in a P-type substrate, a P-type doped region is formed in the N well, and the P-type doped region is used as the first A source, a second source, and a drain; the gate structure on the N well is located between the first source and the second source, and the gate structure has a symmetric structure with respect to the source polysilicon Two storage bits, each containing a floating gate and a wordline gate. The flash memory unit provided by the present invention is programmed by generating high-energy electrons or even hot electrons through the collision ionization of hot holes at the pinch-off point of the drain, which is beneficial to the miniaturization of the device and achieves the purpose of reducing the unit area of ​​the device.

A platinum-silicon nanowire infrared detector comprises a P-type epitaxial silicon substrate layer, a platinum-silicon film photo-sensitive layer, a P-type polycrystalline silicon cap layer and an antireflection film layer. The P-type epitaxial silicon substrate layer, the platinum-silicon film photo-sensitive layer, the P-type polycrystalline silicon cap layer and the antireflection film layer are sequentially overlapped. The platinum-silicon film photo-sensitive layer is a platinum-silicon nanowire, and the platinum-silicon nanowire infrared detector works in a front illumination mode. The platinum-silicon nanowire infrared detector has the advantages that absorptive rate can be increased through the platinum-silicon nanowire, a huge fringing field exists at the top end of the platinum-silicon nanowire to generate an avalanche multiplication effect, and the quantum efficiency of the platinum-silicon nanowire infrared detector is substantially improved; through the P-type polycrystalline silicon cap layer, the escape probability of photoproduction hot holes can be doubled, exchange of movable electric charges and photoproduction free electrons in the antireflection film layer is prevented, noise and dark currents of the platinum-silicon nanowire infrared detector are reduced, the front illumination mode is adopted in the detector, the packaging technology is substantially simplified, and reliability of the detector is improved.

Carrier wafers are used to hold thin and ultra-thin substrates such as semiconductor components, for example. The carrier wafer of the invention has a plurality of electrodes insulated on all sides (floating electrodes). This plurality of floating electrodes, but at least 50 floating electrodes, are located next to one another with reference to the plane of the first surface of the carrier wafer. Each of these floating electrodes can be charged, for example by means of Fowler-Nordheim tunnels or by the injection of hot charge carriers, in particular of hot electrons or hot holes. Also provided are a method for holding a flexible substrate by means of a carrier wafer of this type and a method for the manufacture of a carrier wafer of this type.

The present invention provides a non-volatile memory with optimal memory erasing function and a corresponding method, particularly a method of erasing a non-volatile memory. The non-volatile memory includes a source and a gate. , a drain, a channel and a capture layer. A method according to a preferred embodiment of the present invention includes the following steps: applying a non-zero gate voltage to the gate, applying a non-zero source voltage to the source, and applying a non-zero drain voltage during each erase trigger. The drain voltage is at the drain electrode and the amplitude of the drain voltage is higher than the source voltage, hot holes are generated in the non-volatile memory, and the generated hot holes are injected into the trapping layer near the drain junction. , and the non-volatile memory is erased accordingly. An erasing method according to another embodiment of the present invention includes performing a verification step after each erase firing to verify the memory erasure of the non-volatile memory. If the memory erasure is not verified, repeat the method according to this method. Inventive process steps.