36results about How to "Program disturb" patented technology

A method of programming a nonvolatile semiconductor memory device using a negative bias voltage. The method includes turning ON the string selection transistors connected to selected bit lines and turning OFF the string selection transistors connected to unselected bit lines in the same memory block, in a program mode. This can be achieved by applying a negative bias voltage to a bulk substrate and applying a voltage having a voltage level higher than the threshold voltage of string selection transistors connected to selected bit lines and lower than the threshold voltage of string selection transistors connected to unselected bit lines. The method may reduce programming disturbance between a selected cell string and an unselected cell string.

A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

The invention provides a method for preparing a flash memory. The invention performs oxidation treatment on a semiconductor substrate formed with a tunnel oxide layer before forming a floating gate, so as to enhance the stability of the surface of the active region in contact with the tunnel oxide layer. Simultaneously, the present invention reduces the deposition thickness of the metal layer that prepares metal silicide and carries out the heat treatment that will form metal silicide in two stages, helps to strengthen the stability and the surface uniformity of metal silicide, wherein, the second heat treatment Phase is higher temperature and shorter than the first phase. The present invention uses the above method to prevent the metal silicide from irregularly corroding to the contact surface of the gate structure and the active region, thereby reducing the programming interference caused by the irregular erosion, achieving the purpose of suppressing the programming interference of the flash memory, and further avoiding The reliability of the drain region is reduced during cycle operation, while avoiding the data retention of the flash memory to generate tail bits.

The invention provides a split-gate flash memory unit and a forming method thereof. The split-gate flash memory unit comprises a semiconductor substrate, a source line polycrystalline silicon layer which is located on the surface of the semiconductor substrate, a source electrode which is located in the semiconductor substrate aligned to the source line polycrystalline silicon layer, a coupling oxide layer and a floating gate which are sequentially located on the semiconductor substrate surfaces at two sides of the source polycrystalline silicon layer, a side wall medium layer which is used for electrically isolating the source wire line polycrystalline silicon from the coupling oxide layer and the floating gate, a coupling oxide layer which is located on the side wall of the floating gate far away from the source line polycrystalline silicon layer, an epitaxial layer which is located on the surface of the semiconductor substrate at one side of the coupling oxide layer far away from the source line polycrystalline silicon layer, tunneling oxide layers which are located on the surface of the epitaxial layer and on the side wall of the side medium layer far away from the source line polycrystalline silicon layer, word line polycrystalline silicon layers which are located on the surfaces of the tunneling oxide layers, and drainage electrodes which are located in the epitaxial layer at one side of the word line polycrystalline silicon layer far away from the floating gate and the semiconductor substrate. With the adoption of the split-gate flash memory unit provided by the invention, the programming efficiency of the split-gate flash memory unit can be improved and the miniaturization is easy to realize.

The programming method and programming system of the memory provided by the present invention include: obtaining the selected storage unit and its target storage state, i.e. the i-th state, according to the programming data; The pass voltage on the word line adjacent to the word line of the unit is increased by a preset value; it is judged whether the threshold voltage of the selected memory cell is less than a preset intermediate verification voltage, and the preset intermediate verification voltage is less than the verification voltage of the i-th state and greater than the i-th verification voltage ‑1 state verification voltage; if yes, make the programming pulse step equal to the first step, and program the selected memory cell; if not, make the programming pulse step equal to the second step, and program the selected memory cell The unit is programmed with a second step size smaller than the first step size. Since the pass voltage on the adjacent word lines is increased when programming is started in the present invention, the programming interference of the word line of the selected memory cell to the adjacent word lines can be reduced.

The invention relates to a programming operation method and device for a memory. The memory includes a first input terminal, a first storage string, a second storage string and a second input terminal sequentially arranged in a preset direction. The first storage string includes a series A plurality of first memory cells, the second memory string includes a plurality of second memory cells connected in series, the programming operation method includes: precharging the programming operation, including providing a first preset voltage to the first input terminal, and charging the first The gate layer of the memory cell provides a second preset voltage to precharge the channel in the first memory string; perform a programming operation to program the second memory cell, thereby performing a programming operation on the second memory string When , the charge density of the channel can be effectively reduced in the pre-charging stage of the programming operation, thereby reducing programming disturb.

The application provides a storage system and a programming method. Each word line of the memory is connected to a plurality of storage units, the plurality of storage units include a first storage unit and a second storage unit except the first storage unit, and the programming method includes: performing level 1 programming, so that the first storage unit The threshold voltage of the cell is programmed to be greater than or equal to the final verification voltage of the first memory cell, and the threshold voltage of the second memory cell is programmed to be greater than or equal to the first-level intermediate verification voltage, wherein the first-level intermediate verification voltage of the memory cell is lower than the final verification voltage voltage, the threshold voltage of the first memory cell is greater than the threshold voltage of the second memory cell; and performing Nth level programming, configuring the threshold voltage of a plurality of second memory cells to be greater than or equal to the final verification voltage, where N≥2.

The invention discloses an operation method of a non-volatile memory device. The operation method is suitable for a non-volatile memory device which includes a column decoder and a memory array. The operation method of the non-volatile memory device comprises the following steps of: transmitting a plurality of word signals to the memory array by using the column decoder; switching a selected wordsignal in the plurality of word signals from a preset voltage level to a programming voltage level by using the column decoder according to a bus; switching at least one auxiliary word signal in the plurality of word signals from a preset voltage level to a first pass voltage level by using the column decoder; when the selected word signal is maintained at the programming voltage level, utilizingthe column decoder to switch at least one auxiliary word signal from the first pass voltage level to a second pass voltage level, wherein the second pass voltage level is higher than the first pass voltage level.

A method for reducing programming interference of 3D NAND memory. When programming, a selected memory string is used as a selected string, and other memory strings are used as non-selected strings, and a certain memory cell in the selected string is programmed. Apply a programming voltage on the control gate corresponding to the memory cell to be programmed, use the control gate to which the programming voltage is applied as a selection layer, and control gates of other layers as a non-selection layer; A first bias voltage is applied to at least one of the non-selected layers, and a second bias voltage is applied to the remaining selected layers, the first bias voltage is smaller than the second bias voltage, and the first bias voltage and The second bias voltages are all lower than the programming voltage. The method of the present invention reduces the programming disturbance to the memory cell in the non-selected string which is located in the same layer as the programmed memory cell.

A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.

A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.