36results about How to "Program disturb" patented technology

The invention provides a split-gate flash memory unit and a forming method thereof. The split-gate flash memory unit comprises a semiconductor substrate, a source line polycrystalline silicon layer which is located on the surface of the semiconductor substrate, a source electrode which is located in the semiconductor substrate aligned to the source line polycrystalline silicon layer, a coupling oxide layer and a floating gate which are sequentially located on the semiconductor substrate surfaces at two sides of the source polycrystalline silicon layer, a side wall medium layer which is used for electrically isolating the source wire line polycrystalline silicon from the coupling oxide layer and the floating gate, a coupling oxide layer which is located on the side wall of the floating gate far away from the source line polycrystalline silicon layer, an epitaxial layer which is located on the surface of the semiconductor substrate at one side of the coupling oxide layer far away from the source line polycrystalline silicon layer, tunneling oxide layers which are located on the surface of the epitaxial layer and on the side wall of the side medium layer far away from the source line polycrystalline silicon layer, word line polycrystalline silicon layers which are located on the surfaces of the tunneling oxide layers, and drainage electrodes which are located in the epitaxial layer at one side of the word line polycrystalline silicon layer far away from the floating gate and the semiconductor substrate. With the adoption of the split-gate flash memory unit provided by the invention, the programming efficiency of the split-gate flash memory unit can be improved and the miniaturization is easy to realize.

The invention discloses a control method for reducing programming interference. The method is applied to a memory device. The method comprises the following steps: a first preset potential is loaded on a bottom gate of the memory device in a precharging stage; a second preset potential is loaded on the P well of the memory device; And the first preset potential is lower than the second preset potential so that a potential of a channel hole of the memory device is raised based on a potential difference between the first preset potential and the second preset potential.

The invention discloses a block erasing method for a NAND type flash memory. The method comprises erasing operation, erasing examination operation, soft programming operation and soft programming examination operation. By means of soft programming operation, all memory cells of a block of the NAND type flash memory are programmed together, and time for programming the memory cells can be saved greatly. By means of soft programming examination operation, all the memory cells of the block of the NAND type flash memory are examined together, the operating mode of soft programming examination operation is identical with that of erasing examination operation, and soft programming examination operation is different from erasing examination operation only in bit line discharging time or examination judgment voltage. By the adoption of the method, the threshold voltage distribution of the memory units of the block of the NAND type flash memory can be made compact, sound initial threshold voltage distribution is provided for page programming operation, so that programming time is saved, the channel bootstrap efficiency of page programming operation is improved, and programming disturbance is reduced.

The embodiment of the invention provides a memory control method and device and a storage medium. The method comprises the following steps: carrying out programming operation on the memory, wherein afirst voltage is applied to an unselected top select gate (TSG) of the memory at least in a full-on phase of a program operation, so that the unselected TSG is in an off state, and wherein the first voltage is a negative voltage. According to the embodiment of the invention, the negative voltage is applied to the unselected TSG of the memory in the specific time period of the programming operation; therefore, the voltage of the unselected TSG is ensured to be lower than the threshold voltage of the TSG in the channel boosting period of the programming operation, so that the unselected TSG is in a completely off state, and the unselected TSG is prevented from being mistakenly selected due to the coupling effect of channel boosting. In this way, programming disturbances in the memory are reduced.

The invention discloses a method for reducing programming interference of a 3D NAND memory. The method comprises the following steps of during programming, taking the selected storage string as a selection string; taking a to-be-programmed memory cell as a control grid, taking other memory strings as non-selection strings, programming a certain memory cell in the selection strings, applying a programming voltage to the control grid corresponding to the to-be-programmed memory cell, taking the control grid to which the programming voltage is applied as a selection layer, and taking the controlgrids of other layers as non-selection layers; and selecting at least one of a plurality of non-selection layers which are more than one away from the selection layer to apply first bias voltage, andapplying second bias voltage to the rest of the selection layers, with the first bias voltage being less than the second bias voltage, with the first bias voltage and the second bias voltage being less than the programming voltage. The method provided by the invention reduces programming interference on the memory cell located on a same layer as the programmed memory cell in the non-selection string.

A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.

A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

The invention relates to a programming operation method and device of a memory; the memory comprises a first input end, a first storage string, a second storage string and a second input end which are sequentially arranged in a preset direction; the first storage string comprises a plurality of first storage units which are connected in series, and the second storage string comprises a plurality of second storage units which are connected in series. The programming operation method comprises the steps of performing pre-charging of programming operation, including providing a first preset voltage for a first input end and providing a second preset voltage for a gate layer of a first memory cell so as to pre-charge a channel in a first memory string; performing programming operation to program the second storage unit, so that when the programming operation is carried out on the second storage string, the charge density of a channel can be effectively reduced in the pre-charging stage of the programming operation, and the programming interference is further reduced.

The invention relates to a programming operation method and device of a memory, the memory comprises a first memory string, a first input end and a second input end, the first input end and the second input end are located at the two ends of the first memory string, the first memory string comprises a plurality of first memory cells connected in series, and the programming operation method comprises the following steps: performing pre-charging of a first programming operation, providing a first preset voltage for a second input end, and providing a second preset voltage for a gate layer of a first memory cell in a programmed state, so that the first memory cell in the programmed state is conducted, and a channel in a first memory string is pre-charged; carrying out first programming operation, wherein the first programming operation carries out programming on the multiple to-be-programmed first storage units from the first storage unit close to the second input end to the direction away from the second input end, and therefore when programming operation is carried out on the storage string, the charge density of a channel can be effectively reduced in the pre-charging stage of the programming operation. And the programming interference is further reduced.

The embodiment of the invention discloses a memory, a storage system and a pre-charging method, and belongs to the technical field of storage. The pre-charging method comprises the following steps: applying a pre-charging voltage to a source line connecting end; applying a voltage to the gate of each memory cell in the memory cell stack; wherein the voltage applied to the grid electrode of the programmed storage unit is greater than the threshold voltage of the programmed storage unit, and the voltage applied to the grid electrode of the non-programmed storage unit is greater than the threshold voltage of the non-programmed storage unit. According to the method, the electrons in the doped region and the electrons in the channel of the memory cell coupled with the selected word line can be fully attracted to the source line connecting end under the condition that the programmed memory cell exists in the memory cell stack, so that the non-selected memory string can be fully pre-charged; and the programming interference suffered by the memory unit coupled with the selected word line in the memory unit stack is reduced.

Disclosed herein is a method for inhibiting a programming disturbance of a flash memory, which relates to a technical field of a non-volatile memory in ultra-large-scale integrated circuit fabrication technologies. In the present invention, an dopant gradient of a PN junction between a substrate and a drain is reduced by adding a step of performing an angled ion implantation of donor dopants into a standard process for a flash memory, so that an electric field of the PN junction between the substrate and the drain is reduced, and consequently the programming disturbance is inhibited. Meanwhile, a dopant gradient of the PN junction between a channel and the drain is maintained, so that an electric field of the PN junction between the channel and the drain, which is necessary for programming, is maintained, and thus the programming efficiency and the programming speed can be ensured. The programming disturbance can be effectively inhibited without increasing numbers of masks used for photolithography according to the invention, thus the present invention is significantly advantageous to the improvement of the flash memory reliability.