Method for reducing programming interference of 3D NAND memory

A program interference and memory technology, which is applied in static memory, read-only memory, information storage, etc., can solve problems such as memory unit programming interference, and achieve the effect of reducing programming interference

Active Publication Date: 2019-09-06
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the prior art, when programming a certain memory cell in a certain channel hole, it is easy to cause programming interference to other memory cells in the same layer corresponding to other channel holes

Method used

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  • Method for reducing programming interference of 3D NAND memory
  • Method for reducing programming interference of 3D NAND memory
  • Method for reducing programming interference of 3D NAND memory

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Embodiment Construction

[0031] As mentioned in the background art, in the prior art, when programming a certain memory cell in a certain channel hole, it is easy to cause programming interference to other corresponding memory cells in the same layer in other channel holes.

[0032]To this end, an embodiment of the present invention provides a 3D NAND memory programming method, including: providing a 3D NAND memory, refer to figure 1 , the 3D NAND memory includes: a semiconductor substrate; a stack structure in which the control gate 103 and the isolation layer are stacked on the semiconductor substrate; a number of storage strings 30 running through the stack structure, and each storage string 30 includes a channel Layer 125 and the storage layer 125 located on the sidewall of the channel layer, the position of the storage layer 125 corresponding to the control gate 103 of the corresponding layer is a storage unit 20, so that each storage string has several storage cells distributed along the vertical...

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PUM

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Abstract

The invention discloses a method for reducing programming interference of a 3D NAND memory. The method comprises the following steps of during programming, taking the selected storage string as a selection string; taking a to-be-programmed memory cell as a control grid, taking other memory strings as non-selection strings, programming a certain memory cell in the selection strings, applying a programming voltage to the control grid corresponding to the to-be-programmed memory cell, taking the control grid to which the programming voltage is applied as a selection layer, and taking the controlgrids of other layers as non-selection layers; and selecting at least one of a plurality of non-selection layers which are more than one away from the selection layer to apply first bias voltage, andapplying second bias voltage to the rest of the selection layers, with the first bias voltage being less than the second bias voltage, with the first bias voltage and the second bias voltage being less than the programming voltage. The method provided by the invention reduces programming interference on the memory cell located on a same layer as the programmed memory cell in the non-selection string.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing programming interference of 3D NAND memory. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] The existing 3D NAND memory structure includes: a semiconductor substrate; a stack structure in which a control gate and an isolation layer are stacked on the semiconductor substrate; several channel holes running through the stack structure; a storage structure located in the channel hole, the storage The structure includes a charge storage...

Claims

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Application Information

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IPC IPC(8): G11C16/34
CPCG11C16/3431
Inventor 王明刘红涛魏文喆李伟闵园园
Owner YANGTZE MEMORY TECH CO LTD
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