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Semiconductor structure and forming method thereof

A technology of semiconductor and fin structure, applied in the field of semiconductor structure and its formation

Active Publication Date: 2019-03-05
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Exemplary challenges include growing epitaxial layers on source / drain regions of adjacent FinFETs without fusion with epitaxial layers on different fins, and patterning gate electrodes on adjacent FinFETs in juxtaposition

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0024] A number of implementations of the present disclosure will be disclosed in the following examples. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some known and conventional structures and elements will be shown in a simple and schematic manner in the drawings. Also, the same reference numerals in different drawings may be considered as corresponding elements unless otherwise indicated. These figures are drawn to clearly express the connection relationship between the components in the embodiments, and do not show the actual size of the components.

[0025] In addition, relative spatial terms, such as "below", "lower", "bottom", "upper", and "...

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Abstract

Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source / drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

Description

technical field [0001] The present disclosure relates to a fin field effect transistor device structure and its forming method. Background technique [0002] The manufacture of semiconductor components becomes increasingly difficult as their dimensions shrink. One of the challenges in fabricating these devices is precisely lithographically patterning these structures from different layers. For example, shrinking device pitches make patterning and aligning structures between adjacent FinFETs more challenging. Exemplary challenges include growing epitaxial layers on the source / drain regions of adjacent FinFETs without fusion with epitaxial layers on different fins, and patterning gate electrodes on adjacent FinFETs in juxtaposition. Contents of the invention [0003] According to some embodiments of the present disclosure, a semiconductor device structure is proposed, including a substrate, a first fin structure, a second fin structure, a first epitaxial layer, a second ep...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/10H01L29/78H01L21/336
CPCH01L29/0684H01L29/1033H01L29/66795H01L29/785H01L21/823807H01L29/7848H01L29/161H01L21/823814H01L21/823828H01L21/02236H01L29/66545H01L29/165H01L21/823821H01L27/0924H01L29/41791H01L29/6681H01L29/0653H01L29/0847H01L21/823878H01L21/02532H01L21/02057
Inventor 江国诚王志豪程冠伦
Owner TAIWAN SEMICON MFG CO LTD
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