Memory device

Abstract

A memory device comprises a first memory array, a second memory array, a first bit line driving circuit, a second bit line driving circuit, a first word line driving circuit, a second word line driving circuit, a read-write circuit, a controller, a first reference driving circuit and a second reference driving circuit. The first memory array and the second memory array comprise a plurality of memory units. The first bit line driving circuit and the second bit line driving circuit are used for interpreting a memory bit address and driving a bit line. The first and second word line driving circuits are used for interpreting a memory word address and driving a word line. The read-write circuit is used for reading, writing or resetting the memory unit. The controller is used for switching thefirst memory array and the second memory array to work in a single-memory unit mode or a double-memory unit mode. The first reference driving circuit and the second reference driving circuit are usedfor driving reference lines. The embodiment of the invention can be adjusted to a single-memory unit mode or a double-memory unit mode according to requirements.

Description

technical field [0001] The present disclosure relates to a memory device, in particular to a phase change memory memory device. Background technique [0002] In memory technology, memristive memory includes phase change memory (Phase change memory, PCM), which can change the resistance value of the element through the crystal phase change of its own material, and store information with the change of resistance value. When the material is in a crystalline state, it exhibits a low resistance value, on the contrary, when it is in an amorphous state, it exhibits a high resistance value, thereby storing data such as "1" or "0". [0003] In the prior art, when reading the data of the memory unit in the memory device, the single memory unit is turned on, and the current corresponding to the single memory unit is compared with the reference current to obtain It is determined whether the data stored in the single memory unit is "1" or "0". However, the comparison by the current val...

AI Technical Summary

Problems solved by technology

There are at least two main problems in the existing memory architecture: (1) The reference circuit is located in the read-write circuit, generally a transistor is used to generate a reference current, and the position of the transistor is different from the position of the memory unit (cell) If the value is too large, the currents generated by the positions of different memory cells are slightly different, which causes the value set by the reference current to have different noise margins for judging the data of the memory cell as "1" or "0" noisemargin), can not produce memory optimal effect

The variation mechanism of the resistance of the memory cell is different from that of the transistor, so the reference current cannot accurately and adaptively match the variation of the memory cell

(2) In the prior art, because the read-write circuit is located around the column decoding circuit, when reading the memory unit (cell), due to the loading effect of the bit line, the memory unit farthest from the read-out circuit The reading speed is the slowest, and the specification speed of the entire memory is limited by the slowest memory unit

Images