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A reconfigurable task placement method based on area first and dynamic genetic algorithm

A genetic algorithm and layout method technology, applied in the field of reconfigurable task layout based on area priority and dynamic genetic algorithm, can solve problems such as uncontrollable communication delay of application system, routing congestion of processing units, discarding task modules, etc., and achieve improvement. Defects, increase fault tolerance, improve the effect of solving accuracy

Inactive Publication Date: 2019-03-12
PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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AI Technical Summary

Problems solved by technology

Due to the scarcity of computing resources during the task layout process, resource usage conflicts in the task module will cause the layout to fail
One is that the processing unit where the task module layout is located fails or the routing of the processing unit is congested, which will cause interruption of application program execution and uncontrollable communication delay of the system
Second, the task module uses the same computing resource at the same time or the task module layout exceeds the free computing resource space, which will cause the task module to be discarded during system layout

Method used

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  • A reconfigurable task placement method based on area first and dynamic genetic algorithm
  • A reconfigurable task placement method based on area first and dynamic genetic algorithm
  • A reconfigurable task placement method based on area first and dynamic genetic algorithm

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Embodiment 1

[0044] like figure 1 As shown, this embodiment provides a reconfigurable task layout method based on area priority and dynamic genetic algorithm, including the following steps:

[0045] Step S101, initialize the set of task layout schemes, including the management of free areas and the layout of task modules, and manage the free areas before task module layout;

[0046] In this embodiment, the data requested by the task layout is read into the program of the reconfigurable task layout method based on area priority and dynamic genetic algorithm, the maximum number of iterations K, the population size N, and the individual P are randomly initialized i ,i=1,2...,N.

[0047] The free area refers to an enclosed area that is not covered by the task module and is not a forbidden area, and its area is the number of processing units contained therein. The management of the free area includes two processes of update and selection.

[0048] 1. The process of updating the status informat...

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Abstract

The invention belongs to the technical field of task layout method for embedded software and hardware co-design, In particular, it relates to a reconfigurable task layout method based on area first and dynamic genetic algorithm. The method includes initializing task layout scheme set, including managing idle area and layout of task module. Before task module layout, idle area is managed. Dynamic stochastic genetic algorithm (DSGA) is used to solve the optimal task layout. Dynamic stochastic genetic algorithm (DSGA) adopts random crossover strategy, and dynamic factors dynamically change the crossover probability and mutation probability of the population according to the evaluation index of the current population in the iterative process to select the individuals with adaptive constraints.The global optimal layout scheme is evaluated and the global optimal solution is output. The invention is applicable to a large-scale task layout model of a network-on-chip reconfigurable system witha forbidden area, and can effectively improve the quality of the layout scheme and the system performance.

Description

technical field [0001] The invention belongs to the technical field of task layout method for embedded software and hardware collaborative design, in particular to a reconfigurable task layout method based on area priority and dynamic genetic algorithm. Background technique [0002] A partially reconfigurable system (Partial Reconfigurable System), such as a field-programmable gate array (Field-Programmable Gate Array, FPGA) based on static random access memory, can map tasks performed by hardware to reconfigurable areas and configure and remove them in real time tasks, with high efficiency and flexibility. However, reconfigurable systems introduce hardware computing resource management and task layout problems in the task compilation process, which increases the complexity of system design and application implementation to a certain extent, and has become one of the key issues in the research of partially reconfigurable systems. [0003] A bus-based reconfigurable system l...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06N3/12
CPCG06F9/5027G06F2209/5021G06N3/126
Inventor 殷从月魏帅于洪祁晓峰张兴明宋克谭力波高彦钊
Owner PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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