A debugging system of fpga parameters based on hardware-in-the-loop simulation

Abstract

An FPGA parameter debugging system based on hardware-in-the-loop simulation, which can perform adaptive matching for the real channel changes in the whole process of aircraft flight; use the link planning based on scene simulation to form channel simulation results; form real channel signals through channel simulators and transmit them to Signal receiving processor; and then through the intelligent controller to realize online debugging of FPGA loop parameters. The method can effectively realize the online optimization of FPGA loop parameters, so as to shorten the design and debugging time of the signal processing part.

Description

technical field [0001] The invention relates to an FPGA parameter debugging system based on semi-physical simulation. Background technique [0002] With the rapid development of modern aircraft, the communication system of the whole flight process is faced with problems such as strong interference signal and large Doppler frequency shift, which make it difficult to receive and process the forward signal. Based on this phenomenon, the digital processing capability of the signal receiving and processing equipment is required to be relatively high. With the development of digital communication technology so far, the all-digital phase-locked loop FPGA has three performance indicators such as the difficulty of nonlinear system design, the difficulty of realizing low-pass filtering, and the design parameters that cannot realize the phase-locked range, phase-locked speed and stability of the phase-locked loop. Decoupling control and other issues. [0003] The current general FPGA...

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Problems solved by technology

[0005] The purpose of the present invention is to: overcome the deficiencies in the prior art, provide a kind of FPGA parameter debugging system based on hardware-in-the-loop simulation, solve the FPGA loop parameter debugging process lengthy, time-consuming problems

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