sram test structure

Abstract

The invention relates to an SRAM test structure. The device is used for testing the electric leakage condition of an SRAM memory cell. The device comprises a plurality of standard test units. Each standard test unit comprises a plurality of transistors, multiple metal wires, a first shared contact hole and a second shared contact hole. The drain electrode of the first transmission transistor is insulated from the corresponding metal wire; the drain electrode of the second transmission transistor is insulated from the corresponding metal wire; the metal wire corresponding to the drain electrodeof the first transmission transistor and the metal wire corresponding to the drain electrode of the second transmission transistor are in short circuit and are connected to a first test electrode; the metal wire covered on the first shared contact hole and the metal wire covered on the second shared contact hole are in short circuit and are connected to a second test electrode; the electric leakage condition of the SRAM memory cell is monitored by testing the current between the first test electrode and the second test electrode, so that the isolation between metals on the same layer of the SRAM and the isolation between the metals and the shared contact holes and the like are monitored.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to an SRAM test structure. Background technique [0002] A static random-access memory (Static Random-Access Memory, SRAM) is a type of random-access memory. Static random access memory refers to a memory that stores data that can be kept as long as it is powered on. Static random access memory does not need to refresh the circuit, and it is fast, and is often used as a memory for various integrated circuits. [0003] figure 1 It is a schematic diagram of a 6T SRAM storage unit, which is composed of four NMOS transistors T1, T2, Q5, Q6 and two PMOS transistors Q3, Q4. The input terminals of Q5 and Q3 are connected together with the output terminals of Q6 and Q4, and the input terminals of Q6 and Q4 are connected together with the output terminals of Q5 and Q3 to form a latch. Wherein, T1 and T2 are two transmission tubes. [0004] With the continuous development of semiconductor t...

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Problems solved by technology

[0006] However, as the area of ​​static random access memory (SRAM) continues to shrink, the spacing between metal lines and between metal lines and between metal lines and shared contact holes in SRAM (such as figure 2 (shown in the dotted circle) is also shrinking, and the gap between the metal wire and the metal wire and the contact hole will become the source of SRAM leakage. Isolation / short-circuit conditions between wires and metal lines and between metal lines and contact holes

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