New-type enhanced semiconductor device and preparation method thereof
A semiconductor, enhancement-mode technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem that the selective growth of p-GaN materials is difficult to control, the concentration of holes in the p-GaN layer is not high, and the quality of epitaxial crystals is affected. and other problems, to achieve the effect of high stability, reduced requirements, and high conduction capability
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Embodiment 1
[0055] Such as Figure 12 Shown is a schematic diagram of the device structure of this embodiment, a semiconductor enhancement transistor, including a substrate 1 , a semiconductor epitaxial layer grown on the substrate 1 , a gate 10 , a source 8 and a drain 9 . The epitaxial layer includes, from bottom to top, a nitride nucleation layer 2, a nitride stress buffer layer 3, a nitride channel layer 4, a primary epitaxial nitride barrier layer 5, and a p-type nitride layer 6 and a secondary epitaxial layer. Nitride barrier layer 7 . The p-type nitride layer 6 remains only on the primary epitaxial nitride barrier layer 5 in the region of the gate 10 to realize the pinch-off of the two-dimensional electron gas channel under the gate 10 . The secondary epitaxy has no mask, and the secondary epitaxial nitride barrier layer 7 is grown on the primary epitaxial barrier layer and the p-type nitride layer 6 in the region of the gate 10 .
[0056] The fabrication method of the above-ment...
Embodiment 2
[0070] Such as Figure 13 Shown is a schematic diagram of the device structure of this embodiment, which differs from the structure of Embodiment 1 only in that a layer of AlN space is sandwiched between the nitride channel layer 4 and the primary epitaxial nitride barrier layer 5 in Embodiment 2. The isolation layer 11 has a thickness of 0.3-3 nm. It is used to improve the two-dimensional electron gas characteristics of the channel.
Embodiment 3
[0072] Such as Figure 14 Shown is a schematic diagram of the device structure of this embodiment, which differs from the structure of Embodiment 1 only in that: Embodiment 1 is middle, and part of the primary epitaxial nitride barrier layer 5 outside the gate 10 region is removed, while Embodiment 3 Part of the primary epitaxial nitride barrier layer 5 outside the region of the middle gate 10 remains intact. Compared with Example 1, Example 3 requires a harsher etching scheme, such as more advanced equipment, or self-terminating etching conditions containing oxygen or fluorine.
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