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Design method of multi-mode HEVC video encoder based on two-chip DSP

A technology of a video encoder and a design method, which is applied in the field of multimedia encoding to achieve the effects of parallelizing work, reducing resource occupancy, and reducing the time occupied by core resources

Active Publication Date: 2021-04-27
BEIHANG UNIV
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The downside is that power consumption, cost, and design complexity need to be considered

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  • Design method of multi-mode HEVC video encoder based on two-chip DSP
  • Design method of multi-mode HEVC video encoder based on two-chip DSP
  • Design method of multi-mode HEVC video encoder based on two-chip DSP

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Embodiment Construction

[0049] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0050] In order to improve the encoding speed of the HEVC video encoder and meet the real-time compression encoding requirements of multi-mode video, the present invention proposes a design method for a multi-mode HEVC video encoder based on two-chip DSP. In this method, a HEVC parallel encoding framework based on dual-chip multi-core DSP is firstly designed to make full use of the computing resources of dual-chip multi-core DSP. Secondly, an efficient dual-chip DSP data communication mechanism is designed to realize high-speed transmission of multi-mode coded data between chips and inside chips through SRIO, DMA and EMIF. Finally, a self-checking mechanism of a double-chip DSP encoder is designed. Realize the detection of the abnormal operation of the encoder. The following is a detailed description.

[0051] A kind of multi-mode HEVC video...

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Abstract

The invention discloses a design method of a multi-mode HEVC video encoder based on a double-chip DSP. In this method, a HEVC parallel encoding framework based on dual-chip multi-core DSP is firstly designed, and two DSPs are used to encode the upper and lower half frames of four kinds of videos simultaneously, and the computing resources of dual-chip DSPs are effectively utilized. Secondly, an efficient dual-chip DSP data communication mechanism is designed to realize high-speed transmission of multi-mode coded data between chips and inside chips through SRIO, DMA and EMIF. Finally, a self-inspection mechanism of a dual-chip DSP encoder is designed to detect the abnormal operation of the encoder and ensure the continuous and stable operation of the encoder. The double-chip DSP-based multi-mode HEVC video encoder design method proposed by the present invention can perform multi-mode video encoding on the premise of ensuring the stable operation of the encoder, and can meet the application requirements of real-time encoding of various video images.

Description

technical field [0001] The invention belongs to the field of multimedia coding, and in particular relates to a method for designing a multi-mode HEVC video encoder based on a double-chip DSP, which is a method for designing and implementing a high-efficiency HEVC hardware encoder on a double-chip DSP. Background technique [0002] Based on the H.264 / AVC high profile, the new-generation video coding standard HEVC has doubled the video compression efficiency by adding and improving a variety of coding technologies. Bitrate reduced by 50%. This advantage makes HEVC more favorable for use in high-definition video coding. However, the improvement of encoding performance comes at the cost of increased computational complexity. For embedded devices with limited computing resources, it is difficult for HEVC to be directly applied to these devices. Therefore, on the premise of ensuring the encoding performance of HEVC, how to reduce the computational complexity of HEVC encoding and...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N19/114H04N19/122H04N19/182H04N19/436H04N19/70H04N19/39
CPCH04N19/114H04N19/122H04N19/182H04N19/39H04N19/436H04N19/70
Inventor 王钢李波张永飞张潮
Owner BEIHANG UNIV