Deep trench isolation structure of cmos image sensor and its manufacturing method

Abstract

The invention discloses a deep trench isolation structure of a CMOS image sensor and a manufacturing method thereof. The deep trench isolation structure includes a plurality of isolation structures located between photosensitive regions in a substrate, and each isolation structure It includes a first trench isolation structure and a second trench isolation structure. The first trench isolation structure is formed in the first surface of the substrate, wherein the first trench isolation structure includes a first filling layer and a first dielectric liner covering the surface of the first filling layer. The second trench isolation structure is formed in the second surface of the substrate opposite to the first surface, and the second trench isolation structure includes a second filling layer and a second dielectric liner covering the surface of the second filling layer, wherein The bottom surface of the second dielectric liner is in direct contact with the bottom surface of the first dielectric liner.

Description

technical field [0001] The present invention relates to a complementary metal oxide semiconductor image sensor (CMOS image sensor, CIS) technology, and in particular to a deep trench isolation structure (deep trench isolation, DTI) of a CMOS image sensor and its Manufacturing method. Background technique [0002] The deep trench isolation structure in the CMOS image sensor is used to isolate the light and charge between the CMOS image sensors, so as to reduce the crosstalk between the light and the charge between pixels. [0003] Due to the limitations of the manufacturing process of the conventional DTI, when the pixel size (pixel size) is reduced, its width still occupies a considerable device area. However, such a width makes the area of ​​the photo-sensing region relatively reduced, resulting in a lower full well capacity (FWC). [0004] In addition, a common back side DTI in the prior art cannot extend to the front surface, so it cannot achieve complete isolation, esp...

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Problems solved by technology

[0003] Due to the limitations of the manufacturing process of the existing DTI, when the pixel size (pixel size) is reduced, its width still occupies a considerable device area

However, such a width makes the area of ​​the light-sensing region relatively reduced, resulting in a lower potential well capacity (full well capacity, FWC)

[0004] In addition, a common crystal back-side DTI in the prior art cannot extend to the front surface, so it cannot achieve complete isolation, especially for the crosstalk between long-wavelength light and charges

In addition, when forming the back-end DTI, in order to avoid the components formed on the front side of the chip in the back-end manufacturing process (BEOL) from being affected by high temperature, when forming the back-end DTI, for example, the annealing in the passivation step must be The temperature when controlling the heat transfer to the metal wiring of the BEOL is below 400°C, so it becomes difficult to control the heat source input from the crystal back, and it is difficult to achieve the purpose of high temperature activation of DTI surface doping

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