A semiconductor packaging structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor device, semiconductor/solid-state device components and other directions, can solve the problems of emission, limited contact area of stacked packaging structure, serious heat dissipation, etc., and achieve working stability Good results
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Embodiment 1
[0093] Specifically, such as figure 2 , 3 As shown, this embodiment provides a POP package structure, including: bottom sealing body 100 and a top-seating body 200;
[0094] The base seal is mainly composed of a retraining structure, an electromagnetic interference shielding structure, and at least one chip;
[0095] The retaining wire structure has a first mounting surface, and the electromagnetic interference shielding structure is disposed on the first mounting surface, and the electromagnetic interference shield structure has a housing chamber, and the chip is located in the receiving chamber and is connected to the first mounting surface; The first surface of the structure is provided with a thermally conductive layer between the inner end surface (first surface) of the accommodating chamber, for transmitting heat of the chip to the electromagnetic interference shield structure.
[0096] Specifically, the bottom sealing body 100 is mainly composed of a retraining line struct...
Embodiment 2
[0117] The present invention also provides an embodiment of a method of manufacturing a POP package structure, and specifically comprises: manufacturing a bottom package 100 and a top-seating body 200;
[0118] Manufacturing base package 100 includes:
[0119] Such as Figure 11 , 19 As shown, a first carrier 400 is provided, and a heavy wiring structure 1 is deposited on one side surface of the first carrier 400;
[0120] The first mounting surface 11 of the retaining line structure 1 is solder paste print 15;
[0121] Such as Figure 12 As shown, the open end 22 of the two-end open connection frame portion 24 is connected to the first mounting surface 11, and the chip 4 is placed in the receiving chamber of the connection frame portion 24 and the retaining line structure 1. The first mounting surface 11 is connected by a coefficient of crystal engagement; the relay terminal 8 is implanted on the first mounting surface 11;
[0122] The heat conductive layer 5 is coated on the fir...
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