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A semiconductor packaging structure and manufacturing method thereof

A technology of packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor device, semiconductor/solid-state device components and other directions, can solve the problems of emission, limited contact area of ​​stacked packaging structure, serious heat dissipation, etc., and achieve working stability Good results

Active Publication Date: 2021-03-12
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the small size of the through hole 302, the contact area with the inside of the package-on-package structure is limited, so the heat absorbed by the thermal dielectric material 304 cannot be completely dissipated from the through hole 302, resulting in residual heat inside. When the working time is long, the For the lower chip 303 with increasing power consumption in the bottom package 301, the problem of heat dissipation is even more serious
On the other hand, in the existing package-on-package structure, in order to achieve high functionality, various components are installed inside, but since there is no electromagnetic interference shielding structure, electromagnetic signal interference will occur between components

Method used

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  • A semiconductor packaging structure and manufacturing method thereof
  • A semiconductor packaging structure and manufacturing method thereof
  • A semiconductor packaging structure and manufacturing method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0093] Specifically, such as figure 2 , 3 As shown, this embodiment provides a POP package structure, including: bottom sealing body 100 and a top-seating body 200;

[0094] The base seal is mainly composed of a retraining structure, an electromagnetic interference shielding structure, and at least one chip;

[0095] The retaining wire structure has a first mounting surface, and the electromagnetic interference shielding structure is disposed on the first mounting surface, and the electromagnetic interference shield structure has a housing chamber, and the chip is located in the receiving chamber and is connected to the first mounting surface; The first surface of the structure is provided with a thermally conductive layer between the inner end surface (first surface) of the accommodating chamber, for transmitting heat of the chip to the electromagnetic interference shield structure.

[0096] Specifically, the bottom sealing body 100 is mainly composed of a retraining line struct...

Embodiment 2

[0117] The present invention also provides an embodiment of a method of manufacturing a POP package structure, and specifically comprises: manufacturing a bottom package 100 and a top-seating body 200;

[0118] Manufacturing base package 100 includes:

[0119] Such as Figure 11 , 19 As shown, a first carrier 400 is provided, and a heavy wiring structure 1 is deposited on one side surface of the first carrier 400;

[0120] The first mounting surface 11 of the retaining line structure 1 is solder paste print 15;

[0121] Such as Figure 12 As shown, the open end 22 of the two-end open connection frame portion 24 is connected to the first mounting surface 11, and the chip 4 is placed in the receiving chamber of the connection frame portion 24 and the retaining line structure 1. The first mounting surface 11 is connected by a coefficient of crystal engagement; the relay terminal 8 is implanted on the first mounting surface 11;

[0122] The heat conductive layer 5 is coated on the fir...

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Abstract

The invention relates to a semiconductor package structure and a manufacturing method thereof. The package structure includes a bottom package body with a rewiring structure, and a chip is arranged on a first mounting surface of the rewiring structure; an accommodation chamber of an electromagnetic interference shielding structure and a rewiring structure The first installation surface is connected; a heat conduction layer is arranged between the inner top wall of the containing chamber and the chip. The manufacturing method includes depositing a rewiring structure on the surface of the carrier; connecting the electromagnetic interference shielding frame to the first mounting surface, placing the chip in the electromagnetic interference shielding frame, and planting the terminals on the first mounting surface; coating the chip with a heat conduction layer; forming a plastic package The body is on the first installation surface of the rewiring structure; the metal layer is sputtered on the upper surface of the plastic package; and the terminal is exposed by drilling the plastic package. The packaging structure realizes the heat dissipation of the chip through the electromagnetic interference shielding structure and the heat conduction layer, and shields the electromagnetic signal interference between the components.

Description

Technical field [0001] The present invention relates to the field of semiconductor packaging, and in particular, to a semiconductor package structure and a method of manufacturing the same. Background technique [0002] With the continuous development of high-density, multi-function, low power, miniaturization, using three-dimensional integrated technology system-level package, SYSTEM IN PACKAGE (SIP) has achieved a sharp development. Among them, the existing three-dimensional integrated technology has been unreasonable due to unreasonable structural design, and the problem of electromagnetic signal interference and heat dissipation effect is prone to reduce the work efficiency and working performance of the device. E.g figure 1 As shown, the existing stacked package structure includes an electrically connected top-seating body 300 and a bottom package 301, and a through hole 302 having a through-top cover 300 is opened on the top-seating body 300, and the through hole 302 is pe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/498H01L21/56
CPCH01L21/561H01L23/3128H01L23/49811H01L23/49827H01L2224/16225H01L2224/48227H01L2224/73253H01L2224/73265H01L2924/15311H01L2924/181H01L2924/00012
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC