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A memory optimization type static time sequence analysis method and system

A static timing analysis, memory technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as large memory consumption, reduce the number of tags, reduce space requirements, and improve analysis efficiency.

Active Publication Date: 2019-05-03
SHANGHAI ANLOGIC INFOTECH CO LTD
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Problems solved by technology

The operating efficiency of the underlying engine, including running time and space consumption, becomes the bottleneck of the efficiency of the whole set of tools. The inventors of this application have observed that the most cutting-edge static timing analysis method in the prior art can eliminate false paths and clarify multi-cycle paths. There is a problem with excessive memory consumption

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  • A memory optimization type static time sequence analysis method and system
  • A memory optimization type static time sequence analysis method and system
  • A memory optimization type static time sequence analysis method and system

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Embodiment Construction

[0055] In the following description, many technical details are proposed in order to enable readers to better understand this application. However, those of ordinary skill in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in this application can be realized.

[0056] Explanation of some concepts:

[0057] 1. Static sequence analysis: In electronic engineering, the sequence of digital circuits is calculated and predicted. The process does not need to be simulated by input excitation. Traditionally, people often regard the operating clock frequency as one of the characteristics of high-performance integrated circuits. In order to test the ability of a circuit to operate at a specified rate, people need to measure the delay of the circuit in different stages of operation during the design process. In addition, in different design stages (such as logic synthesis,...

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Abstract

The invention relates to a digital circuit, and discloses a memory optimization type static time sequence analysis method and system. According to the method, on the premise that the subgraphs are notexpanded, in the traversing and scanning process, false paths are identified and discarded in real time, the influence of the false paths on downstream nodes is reduced, redundant calculation is reduced, meanwhile, multiple time sequence constraints on each node are dynamically and differentially processed in the traversing process, dichotomy coverage is correspondingly carried out, and the number of labels on each node is reduced. According to the application, occupation of system memory space can be greatly reduced, the system operation efficiency is improved, and the system performance isimproved.

Description

Technical field [0001] This application relates to the field of digital circuits, in particular to a memory optimized static timing analysis method and system. Background technique [0002] In the process of physical design and realization of digital circuits, static timing analysis plays a very important role, and its feedback results provide drivers for the multi-channel optimization program in this process. In different design stages, such as logic synthesis, placement and routing, etc. , The core of the tool repeatedly calls static timing analysis and iterative optimization. Therefore, as a crucial underlying analysis engine, the performance of static timing analysis tools has a very important impact on the performance of the entire software tool. The operating efficiency of the underlying engine, including running time and space consumption, has become a bottleneck for the efficiency of the entire set of tools. The inventor of this application has observed that the most cut...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 朱春谢丁
Owner SHANGHAI ANLOGIC INFOTECH CO LTD
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