A fdsoi thyristor electrostatic protection device
A technology of electrostatic protection and devices, which is applied in the field of FDSOI thyristor electrostatic protection devices, can solve the problems of small current magnification, device burnout, high trigger voltage, etc., so as to improve electrostatic protection ability, positive feedback strength, and P well The effect of potential
Active Publication Date: 2021-07-30
48TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
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Problems solved by technology
However, the bulk silicon thickness of FDSOI devices is very thin, and the N+ implantation and P+ implantation regions are deep into the surface of the buried oxide layer, so the positive feedback structure formed has a small current amplification factor
In addition, the trigger point of the traditional FDSOI electrostatic protection device is located at the junction of the P well and the N well, which has a high trigger voltage. When the trigger voltage exceeds the source-drain breakdown voltage of the device, the device will be burned and cannot be effectively discharged. electric current
[0004] It can be seen that the electrostatic protection ability of the existing FDSOI devices is weak and cannot effectively protect the core devices and circuits
Method used
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Embodiment 1
[0032] An FDSOI-controllable silicon electrostatic protection device of the present invention, embedded GGNMOS and GDPMOS, such as image 3 As shown, equivalent circuit diagram is like Figure 7 As shown, a substrate 01 is provided, and an embedding layer 02 is provided on the substrate 01, and an N-well 11 and a P-well 12 are provided, the N-well 11 and the P-well 12 adjacent, image 3 The N well 11 is located on the left side of the P well 12.
[0033] A first P + injection region 13 is provided in the N well 11, and the P-well 12 is provided with a first N + injection region 15, the first P + injection region 13, the N well 11, a p-well and a first N + injection. Region 15 forms a PNPn knot, a cross-sectional view of its structure Figure 4 Indicated.
[0034] The N-well 11 is fitted with the junction of the P-well 12, and the second P + injection region 17 and the second N + injection zone 18, that is, the second P + injection zone 17 is located in the N well 11, and part is locat...
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The invention discloses an FDSOI thyristor electrostatic protection device embedded with GGNMOS and GDPMOS, comprising an N well and a P well, the N well and the P well are adjacent, the N well is provided with a first P+ injection region, and the P well is provided with The first N+ injection region, the junction of the N well and the P well is embedded with a second P+ injection region and a second N+ injection region. Based on the full dielectric isolation characteristics of FDSOI, the invention embeds GGNMOS and GDPMOS into the SCR path, thereby improving its electrostatic discharge efficiency, and has the advantages of low trigger voltage, high sustain voltage, simple structure, and easy integration, and is suitable for FDSOI devices And electrostatic protection of the circuit.
Description
Technical field [0001] The present invention relates to the field of integrated circuit electrostatic protection, relating to an FDSOI thyristor electrostatic protection device, and more particularly to an FDSOI-controllable silicon electrostatic protection device of embedding GGNMOS and GDPMOS. Background technique [0002] With the development of Moore's law, the integration of chips is constantly improving, and power consumption and performance have been greatly improved. However, after the body silicon technology has developed to 28 nm, the technical complexity and manufacturing cost have greatly improved, and the full-depletion type insulator (FDSOI) came into being. Under the same technical node, FDSOI technology can effectively reduce manufacturing processes, reduce chip power consumption, improve product yield, and have strong radiation resistance. Due to the advantages of price, power and performance, FDSOI has gradually become mainstream in applications such as Internet...
Claims
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IPC IPC(8): H01L27/02
Inventor 丁玎谢峰何峰曾庆平
Owner 48TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP