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Word line decoding circuit, sram and forming method

A word line decoding and circuit technology, applied in the field of word line decoding circuits, can solve problems such as slow access rate of SRAM

Active Publication Date: 2021-02-09
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Description
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Problems solved by technology

However, in this way, the reduction of this period of time is limited, and the access rate of SRAM is still relatively slow

Method used

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  • Word line decoding circuit, sram and forming method
  • Word line decoding circuit, sram and forming method
  • Word line decoding circuit, sram and forming method

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Embodiment Construction

[0029] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0030] At the same time, it should be understood that, for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0031] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way taken as any limitation of the invention, its application or uses.

[0032] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the...

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Abstract

The invention discloses a word line decoding circuit, an SRAM and a forming method, and relates to the technical field of semiconductors. The word line decoding circuit includes: a NAND gate unit, a first inverter and a capacitor; the capacitor includes: a first end and a second end, wherein the first end of the capacitor is connected to the NAND gate unit The output terminal of the capacitor is connected, and the second terminal of the capacitor is connected with the output terminal of the first inverter. In the present invention, by setting a capacitor between the output terminal of the NAND gate unit and the output terminal of the first inverter, capacitive coupling is used to promote the inversion of the clock control signal output by the first inverter When the signal falls from the high level to the low level, it can promote the rapid decline of the NAND output result signal of the NAND gate unit, thereby increasing the access rate of the SRAM.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a word line decoding circuit, SRAM (Static Random Access Memory, static random access memory) and a forming method. Background technique [0002] Currently, SRAM has been widely used in portable devices and high-performance processors. SRAM with high speed and low power consumption is a hot spot of current research. Improving the access speed of SRAM is of great significance to the whole system. In the SRAM access time, the time from the rise of the clock signal CLK to the turn-on of the word line selection signal WL (that is, the rise of the word line selection signal WL from low level to high level) occupies a large proportion. It is of great significance to increase the speed of the entire SRAM. [0003] Generally, the SRAM includes a word line decoding circuit (also called a row address decoding circuit). figure 1 It is a circuit connection diagram schematic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/418G11C8/10
Inventor 方伟史增博
Owner SEMICON MFG INT (SHANGHAI) CORP
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