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Address scheduling method of nonvolatile memory device with three-dimensional memory cell array

A technology of non-volatile storage and storage unit, which is applied in the field of address scheduling of 3D storage unit array, and can solve the problem of reducing the operating speed of the device

Pending Publication Date: 2019-05-14
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these address scheduling methods may slow down device operation

Method used

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  • Address scheduling method of nonvolatile memory device with three-dimensional memory cell array
  • Address scheduling method of nonvolatile memory device with three-dimensional memory cell array
  • Address scheduling method of nonvolatile memory device with three-dimensional memory cell array

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Embodiment Construction

[0025] figure 1 is a block diagram illustrating a nonvolatile memory system 100 according to at least one example embodiment of the inventive concept. The nonvolatile memory system 100 may include a nonvolatile memory device 120 and a memory controller 110 controlling the nonvolatile memory device 120 . The nonvolatile memory device 120 may be a NOR flash memory and / or a NAND flash memory, but example embodiments are not limited thereto. The nonvolatile memory device 120 may include a memory cell array 230, a row decoder 240, a write driver / sense amplifier (SA) circuit 250, a control circuit 260, a voltage generator 270, and an input / output (I / O) circuit 280. .

[0026] The row decoder 240 may select one word line from a plurality of word lines in response to a row address, may apply a first operating voltage to the selected word line, and may apply a second operating voltage to unselected word lines. For example, the row decoder 240 may apply a first operating voltage (eg...

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PUM

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Abstract

The at least one address scheduling method comprises the following steps: selecting a first bit line; selecting a first string connected to the first bit line; sequentially executing address scheduling of N pages of each multi-level unit in the first string from the bottom word line to the top word line; after address scheduling on all word lines in the first string is completed, address scheduling is sequentially performed on the second to kth strings in the same manner as performed on the first string, where "k" is a natural number of 2 or greater.

Description

technical field [0001] Example embodiments relate to an address scheduling method for a three-dimensional (3D) memory cell array, and more particularly, to an address scheduling method for a 3D memory cell array in a nonvolatile memory device including a plurality of multi-level cells. Background technique [0002] Flash memory used as electrically erasable programmable read only memory (EEPROM) may have advantages of random access memory (RAM) that can easily program and erase data and ROM that can retain data without power supply. [0003] Flash memory is generally divided into NAND flash memory and NOR flash memory. The NOR flash memory may have a structure in which memory cells are independently connected to bit lines and word lines, thereby having excellent random access time characteristics. On the other hand, NAND flash memory can be improved in terms of integration because it has a structure in which multiple memory cells can be connected to each other so that only ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/08G11C16/10
Inventor 尹治元南尚完尹廷允蔡东赫
Owner SAMSUNG ELECTRONICS CO LTD