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Driving enhancement type pixel structure suitable for a large-area-array CMOS image sensor

An image sensor and drive enhancement technology, which is applied in the direction of image communication, color TV parts, TV system parts, etc., can solve problems such as limited effects, and achieve the effect of reducing the influence of parasitic effects

Inactive Publication Date: 2019-05-21
TIANJIN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The method adopted at this stage is mainly to reduce the width of the metal line and try to carry out the metal wiring on the upper layer to reduce the parasitic effect, but for the pixel array with less available metal layers, the effect is very limited

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  • Driving enhancement type pixel structure suitable for a large-area-array CMOS image sensor
  • Driving enhancement type pixel structure suitable for a large-area-array CMOS image sensor
  • Driving enhancement type pixel structure suitable for a large-area-array CMOS image sensor

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Embodiment Construction

[0016] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0017] The invention is realized on the basis of the traditional 4T pixel structure, which can change the non-working state pixels into relay SF, realize pixel SF multiplexing, cut the too long column bus into multiple segments, and drive in segments, which can effectively reduce the column bus parasitic The effect of capacitance on signal transmission delay.

[0018] As shown in the figure, the drive-enhanced pixel structure applicable to a large area array CMOS image sensor of the present invention includes: N-type MOS transistors M1-M7, M1 is a pixel transmission transistor, M2 is a reset transistor for an FD node, and M6 is a source level Follower (sourcefollower, SF), M7 is the ...

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Abstract

The invention discloses a driving enhancement type pixel structure suitable for a large-area-array CMOS image sensor. The driving enhancement type pixel structure comprises an N-type MOS transistor M1-. Wherein M7 and M1 are pixel transmission tubes, M2 is a reset tube of an FD node, M6 is a source follower, M7 is a pixel gating tube, and M3-is a reset tube of an FD node; M5 is a switching tube, the source end of the M1 is connected with a photodiode; Drain termination FD node, The source end of the M2 is connected with an FD node, the drain end of the M3 is connected with an FD node, the drain end of the M4 is connected with the source end of the M6, the drain end of the M6 is connected with a power VDD, the source end of the M7 is connected with a drain end of the M7, and the drain end of the M5 is connected with a node A, a node B and a node M4. According to the invention, pixel SF multiplexing and multistage SF column bus circuit structure can be realized, parasitic capacitance canbe driven in a segmented manner, and the influence of parasitic effect is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a drive-enhanced pixel structure suitable for large area array CMOS image sensors. Background technique [0002] In the field of CMOS image sensors, the larger the pixel array, the higher the resolution, the better the photo effect and the more delicate the image. With the development of aerospace and military industries, CMOS image sensors are gradually being applied to space detection fields such as remote sensing cameras and star sensors. The need for high-resolution image sensors is becoming more and more urgent, and the pixel volume is gradually developing to the billion level. . [0003] Such as figure 1 As shown, for a large area array CMOS image sensor, the output line of the source follower (source follower, SF) is very long, accompanied by a large parasitic resistance and parasitic capacitance effect, when the floating diffusion (floating diffusion, FD) no...

Claims

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Application Information

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IPC IPC(8): H04N5/374H04N5/3745
Inventor 高静张德志聂凯明徐江涛史再峰
Owner TIANJIN UNIV