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Cascade weight sorting system with delay measurement structure

A weight division and cascading technology, applied in general control systems, control/regulation systems, instruments, etc., can solve the problems of increased complexity of wiring work, increased difficulty and cost of system design, and high performance requirements, so as to reduce the number of host interfaces , convenient visual operation, and the effect of relieving communication pressure

Pending Publication Date: 2019-05-24
TECHIK INSTR SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The mechanism of the current weight sorting machine adopts a single main controller for logic control, and a large number of IO ports are centrally controlled by the main machine, which greatly increases the complexity of the wiring work. At the same time, a large amount of power consumption is concentrated on the main machine. The reliability of the power supply system is very fatal. At the same time, due to the large number of control IO ports of the host, the task load of the host is very large, which requires the performance requirements of the MCU to be higher and higher, which greatly increases the difficulty and cost of system design.

Method used

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  • Cascade weight sorting system with delay measurement structure
  • Cascade weight sorting system with delay measurement structure

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Embodiment

[0020] Such as figure 1 As shown, a cascaded weight sorting system with a delay measurement structure includes a master station 1 and multiple slave stations 2, the master station 1 is connected to the weight detection equipment, and the slave station 2 is connected to the mechanical action switch. The system is distributed In the architecture, the master station 1 communicates with multiple slave stations 2 sequentially in series.

[0021] Such as figure 2 As shown, the slave station 2 includes a logical control unit 21, a data transceiving unit (comprising a data transmitting unit 22 and a data receiving unit 23), a counting unit 24 and a clock unit 25 connected in sequence. After the data transceiving unit receives data, the logical control unit 21 performs ID matching, and sends data to the next-level slave station 2 according to the matching result, or performs mechanical actions, and returns the delayed data generated by the counting unit 24 and the clock unit 25 to th...

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Abstract

The invention relates to a cascade weight sorting system with a delay measurement structure. The system comprises a master station and a plurality of slave stations, the master station is connected with weight detection equipment, and the slave stations are connected with mechanical motion switches. The system is in a distributed architecture, the master station and the slave stations are communicated sequentially by means of series connection. Each slave station comprises a logic control unit, a data transceiving unit, a counting unit and a clock unit in sequential connection, wherein after the data transceiving unit receives data, the logic control unit performs ID matching and sends the data to the next slave station according to a matching result or executes mechanical actions and returns delay data generated by the counting unit and the clock unit to the master station. Compared with the prior art, the system has advantages that the slave stations are provided with the counting units and the clock units, delay data can be obtained, and accordingly delay parameter measurement can be realized when propagation delay is sent to a mainframe.

Description

technical field [0001] The invention relates to a weight sorting machine, in particular to a cascade weight sorting system with a delay measurement structure. Background technique [0002] The weight sorter is a mechanical device for grading and screening products by weight. It can screen products in different weight ranges to different assembly lines, saving money and time for manual operations. The mechanism of the current weight sorting machine adopts a single main controller for logic control, and a large number of IO ports are centrally controlled by the main machine, which greatly increases the complexity of the wiring work. At the same time, a large amount of power consumption is concentrated on the main machine. The reliability of the power supply system is very fatal, and at the same time, due to the large number of control IO ports of the host, the task of the host is very large, which requires the performance requirements of the MCU to be higher and higher, which ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/042
Inventor 徐盛龙牟翔施利辉徐光东幸波
Owner TECHIK INSTR SHANGHAI
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