A method for reducing nvme SSD response delay affecting the writing speed of high-speed data storage devices
A response delay and high-speed data technology, applied in the storage field, can solve problems such as data loss and affecting the continuous writing speed of storage devices, and achieve the effects of reducing device power consumption, ensuring continuous data writing speed, and shortening the development cycle
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
specific Embodiment approach 1
[0021] Specific implementation mode one: combine figure 1 This embodiment is specifically described. A method for reducing the NVMeSSD response delay affecting the writing speed of a high-speed data storage device described in this embodiment includes:
[0022] Data cache is performed through the Block RAM of the master FPGA module, which is used to temporarily store the data received during the inherent response delay and other response delays less than 1ms;
[0023] The data storage module is implemented with at least two NVMe SSDs, and the NVMe host controlling the FPGA module controls each NVMe SSD to perform write operations in turn; and when the amount of data written to the current NVMe SSD reaches the preset threshold, a shutdown command is sent to the current NVMeSSD to trigger Mapping table refresh command.
[0024] The response delay of NVMe SSD can be divided into two types: inherent response delay and additional response delay. NVMe SSD is composed of Flash stor...
specific Embodiment approach 2
[0037] Embodiment 2: This embodiment is a further description of a method for reducing the NVMe SSD response delay affecting the writing speed of high-speed data storage devices described in Embodiment 1. In this embodiment, there are two NVMe SSDs.
[0038] Two 970EVO 2TB NVMe SSDs are used for ping-pong operations to avoid write channel blocking caused by a single NVMe SSD with an additional response delay greater than 1ms.
[0039] The high-speed storage device often writes a large amount of data during the application process, and the total amount of written data corresponding to the write command will be very large. In order to facilitate management, the write command is split into multiple write data in the main control FPGA module. 2GByte subcommands. To facilitate management, mark the NVMe SSD that is being written as busy and the other NVMe SSD as idle. When the amount of data written to a busy NVMe SSD reaches a preset threshold, it switches to an idle NVMe SSD to e...
specific Embodiment approach 3
[0040] Specific implementation mode three: combination figure 2 with image 3 This embodiment is specifically described. This embodiment is a further description of a method for reducing the NVMe SSD response delay affecting the writing speed of high-speed data storage devices described in the second embodiment. In this embodiment, the NVMe host controls each NVMe The method for SSDs to perform write operations in turn includes the following steps:
[0041] Step 1: Power on the high-speed data storage device, release the reset signal of the first NVMe SSD, turn on the first NVMe SSD, and the NVMe host sends an initialization command to the first NVMe SSD to obtain the status information of the first NVMe SSD. The NVMe host marks the first NVMe SSD as busy, and the second NVMe SSD as idle, waiting to receive write commands;
[0042] Step 2: After receiving the write command, split the total write command into multiple subcommands with a write data volume of 2GByte;
[0043]...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More