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Manufacturing method of self-aligned double patterning semiconductor structure

A double-patterning and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of self-aligned double-layer pattern and morphology, which are difficult to control, reduce precision requirements, improve yield, The effect of reducing production costs

Inactive Publication Date: 2019-06-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

[0004] The object of the present invention is to provide a method for fabricating a self-aligned double patterned semiconductor structure, so as to solve the need for two exposures before and after the existing self-aligned double patterned semiconductor structure method, which eventually leads to the self-aligned double patterned semiconductor structure formed later. The problem that the shape of layer graphics is difficult to control

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  • Manufacturing method of self-aligned double patterning semiconductor structure
  • Manufacturing method of self-aligned double patterning semiconductor structure
  • Manufacturing method of self-aligned double patterning semiconductor structure

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Embodiment Construction

[0028] As mentioned in the background art, the existing self-aligned double-layer patterning process requires two exposures, which finally leads to the problem that the morphology of the self-aligned double-layer pattern formed later is difficult to control. In the existing self-aligned double patterning process, a semiconductor substrate is first provided, and a film to be etched, a core pattern film and a core pattern formed in the first size are sequentially formed on the semiconductor substrate from bottom to top. Photoresist layer A; using the patterned photoresist layer A as a mask to etch the core pattern film to obtain a first-size core pattern layer; forming sides on both sides of the first-size core pattern layer wall, and remove the core pattern layer of the first size; form a photoresist layer B with a photolithography pattern of the second size on the film to be etched, and use the sidewall and the photoresist layer B as a mask film, etching the film to be etched,...

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Abstract

The invention discloses a manufacturing method of a self-aligned double patterning semiconductor structure, which includes the following steps: providing a semiconductor substrate on which a film to be etched, a core pattern film and a patterned first photoresist layer are formed in sequence; etching the core pattern film with the first photoresist layer as a mask to form a first-size core patternlayer and a second-size core pattern layer; forming spacers on both sides of the first-size core pattern layer and the second-size core pattern layer; forming a second photoresist layer covering thesecond-size core pattern layer; removing the first-size core pattern layer and the second photoresist layer; etching the film to be etched with the spacers and the second-size core pattern layer as amask; and removing the spacers and the second-size core pattern layer to form a self-aligned double pattern. The manufacturing method of the invention has simple process steps, and solves the problemthat it is difficult to control the shape of the self-aligned double pattern because it is difficult to control the nesting accuracy during alignment of the second-size core pattern layer with the first-size core pattern layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a self-aligned double patterned semiconductor structure. Background technique [0002] In semiconductor integrated circuits, with the continuous reduction of the feature size of semiconductor technology, in order to improve the integration of semiconductor devices, a variety of double-layer patterning processes have been proposed in the industry. Among them, self-aligned double patterning (Self-Aligned Double Patterning, SADP ) process is one of them. [0003] In the prior art, when two core pattern layers of different sizes are formed on the same core layer in a semiconductor device, the small-size core pattern and the large-size core pattern must undergo two exposure processes before and after, that is, after forming the small When a core pattern with a small size and a core pattern with a large size need to be formed separately, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/027H01L21/033
Inventor 叶滋婧
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP