A pre-emphasis debugging system and method

Abstract

The invention discloses a pre-emphasis debugging system and method, relates to the field of high-speed serial data communication and the system comprises a PCB (Printed Circuit Board) and an FPGA (Field Programmable Gate Array) chip, each transmitting port of the FPGA chip is connected with a transmitting end radio frequency coaxial head, and the FPGA chip also comprises a PRBS code element generator which is used for generating PRBS code streams of different types and transmitting the PRBS code streams from the transmitting ports; The receiving end radio frequency coaxial head is connected with each transmitting end radio frequency coaxial head through a coaxial cable, and is also connected with a receiving port; The PRBS code element checker checks the PRBS code stream received by the receiving port and calculates the bit error rate; The pre-emphasis management module generates a group of pre-emphasis configuration parameters each time and transmits the pre-emphasis configuration parameters to a sending port, and a PRBS code element generator is started; And the pre-emphasis configuration module is also used for comparing each bit error rate with the previous bit error rate and storing the same bit error rate, the smaller bit error rate and the corresponding pre-emphasis configuration parameters. According to the method, an external test instrument is not needed, the optimalsending end pre-emphasis parameter is automatically tested, and redundant lines are not increased.

Description

technical field [0001] The invention relates to the field of high-speed serial data communication, in particular to a pre-emphasis debugging system and method. Background technique [0002] In a high-speed data communication system, an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is usually used as a high-speed data processing unit, and the FPGA transceiver is an interface unit for high-speed data reception and transmission. With the increase of the signal rate, the skin effect of the high-speed signal and the dielectric loss of the transmission line cause the signal to be greatly damaged during the transmission process. In order to obtain a better waveform at the receiving terminal, it is necessary to compensate the damaged signal. . [0003] A compensation technique commonly used at the sending end includes a pre-emphasis technique. By adjusting the pre-emphasis parameters at the sending end of the FPGA transceiver, the loss of the high-speed signa...

AI Technical Summary

Problems solved by technology

This method has disadvantages when using it. It is necessary to make a test line that is the same as the signal link of the FPGA sending end during PCB design. When using a network analyzer, the pre-designed test line is tested, so there is redundancy on the PCB. The line increases the area of ​​the PCB, and if there are multiple sending ends, it is not accurate to refer to one S parameter because of the different wiring.

[0005] At the same time, the above two commonly used methods require the use of external test instruments to assist in the analysis, which increases the cost and complexity of the test

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