Semiconductor memory cube with enhanced side wall flatness

Abstract

The present invention discloses a semiconductor cube. The semiconductor cube comprises one or more than one highly flat vertical side walls, and electric tracing line patterns are formed on the vertical side walls. The semiconductor cube can be manufactured by a semiconductor cube module, and the semiconductor cube module comprises a vertical semiconductor bared core stack body and a lead bondingbody landing block pair, the vertical semiconductor bared core stack body is bonded to different level of the first and second bonding body landing blocks from first and second relative edge leads, and the semiconductor cube module can be encapsulated in a moulding compound. The moulding compound is cut off to separate the semiconductor bared core stack body from the lead bonding body landing blocks, and a lead bonding body exposed in the side walls of the semiconductor cube module is remained.

Description

technical field [0001] The technology relates to a semiconductor cube and a manufacturing method thereof. Background technique [0002] Strong growth in demand for portable consumer electronic devices is driving the demand for high capacity storage devices. Nonvolatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the increasing demand for digital information storage and exchange. Their portability, versatility, and rugged design together with their high reliability and large capacity have made such memory devices ideal for a wide range of electronic devices including, for example, digital cameras, digital music players, video game consoles, PDAs, and cellular telephones. ) is ideal. [0003] Although many and varied packaging configurations are known, a recent design involves a semiconductor flash memory cube having an array of vertically stacked semiconductor die. The die bond pads of these die extend out to the verti...

AI Technical Summary

Problems solved by technology

In particular, in the formation of electrical trace patterns on vertical edges, if the dies do not come together to form a highly aligned planar surface, the trace patterns may not form properly on the edges and may not function properly

Given that there are manufacturing tolerances in the size of the semiconductor die, and given that the semiconductor die are stacked with DAF layers, which may allow the die to move slightly relative to each other prior to curing, it is difficult to provide vertical edges with the required level of flatness

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