Chip scale package structures

Abstract

The present invention discloses a chip scale package structure. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area ofthe chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds the first redistribution layer of the image sensor chip.

Description

Technical field [0001] The invention relates to a wafer level chip size package (WLCSP) structure. Background technique [0002] The packaging manufacturing process of the traditional image sensor module is based on wire-bonding packaging or chip-scale packaging (CSP). For the overall image sensor module system, the memory chip and control chip are still needed for data access and control. Therefore, the image sensor, memory chip and control chip are usually assembled and integrated on the system board. The communication between the memory chip, the control chip and the image sensor is carried out through this system board. [0003] Recently, due to the innovation in the manufacturing process of image sensors and the substantial increase in pixels, the demand for huge amounts of data access and control has increased. For traditional system integration methods, it is not enough to deal with market trends. Therefore, some companies have developed an assembly technology that integr...

AI Technical Summary

Problems solved by technology

However, this technology still has its bottleneck. To achieve chip-to-chip bonding assembly technology, for now, it can only be applied to small sensors

The reason is that although the chip pitch of the memory chip / logic chip can be adjusted to match the pitch of the image sensor as much as possible, however, when the area of ​​the sensor continues to increase, the chip pitch of the memory chip / logic chip will inevitably increase accordingly. At this time, the number of memory chips / logic chips per unit wafer area will decrease, resulting in a significant increase in overall wafer cost

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