Excitation generation device, chip verification device and chip verification system

A technology for generating devices and verifying devices, which is applied in the field of verification, can solve problems such as difficulty in improving the coverage rate, and achieve the effect of improving the coverage rate and improving the efficiency of chip verification
CN109992804AActive Publication Date: 2019-07-09CAMBRICON TECH CO LTD
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
CAMBRICON TECH CO LTD
Publication Date
2019-07-09

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Abstract

The invention relates to an excitation generation device, a chip verification device, a chip verification system. The excitation generation device comprises a random constraint file generation module,which is used for randomly generating a constraint file according to information to be verified of a chip; a template library used for storing the constraint file; an analysis module used for analyzing the constraint file to obtain a first constraint condition; a condition adjustment module used for adjusting a first constraint condition in the constraint file to obtain a second constraint condition; and an excitation generation module used for generating verification excitation according to the first constraint condition or the second constraint condition. According to the excitation generation device, more diverse excitation generation mechanisms can be provided, more types of verification excitation can be obtained, comprehensive chip verification is facilitated, the coverage rate canbe rapidly increased, and the chip verification efficiency is improved.
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Description

technical field

[0001] The invention relates to the technical field of verification, in particular to an incentive generation device, a chip verification device and a system. Background technique

[0002] One of the purposes of chip verification is to detect bugs in the programs running on the chip. During chip verification, the RTL emulator (Register Transfer level simulation) and the verification model of the chip verification system execute the verification stimulus generated by the stimulus generation device, output the execution result, and the processor of the chip verification system obtains the coverage data according to the output result, and Determine whether the chip verification is terminated according to whether the obtained coverage data meets expectations. Coverage data is a quantitative indicator used to evaluate the verification process and results.

[0003] At present, the mechanisms that generate incentives when using the chip verification system for chi...

Claims

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