Information processing system, semiconductor integrated circuit, and information processing method

An information processing system and integrated circuit technology, which is applied in the field of information processing systems, can solve the problems of not waiting, limiting the high-speed cluster, etc., and achieve the effect of high-speed processing

Pending Publication Date: 2019-07-09
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when Ethernet is used, there is a problem that there is a protocol overhead such as that the next transmission cannot be performed until the t

Method used

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  • Information processing system, semiconductor integrated circuit, and information processing method
  • Information processing system, semiconductor integrated circuit, and information processing method
  • Information processing system, semiconductor integrated circuit, and information processing method

Examples

Experimental program
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Example

[0023] (First embodiment)

[0024] figure 1 It is a diagram showing an example of the information processing system of the first embodiment.

[0025] The information processing system 10 has semiconductor integrated circuits 11 and 12, switches 13, and memories 14, 15.

[0026] The semiconductor integrated circuits 11 and 12 and the switch 13 are each, for example, a one-chip SoC. in figure 1 In order to simplify the description, two semiconductor integrated circuits 11 and 12 and one switch 13 are shown, but the number is not limited to this. An example of an information processing system having three or more semiconductor integrated circuits and two or more switches will be described later.

[0027] The semiconductor integrated circuit 11 has a control circuit 11a, an interrupt control circuit 11b, an address conversion circuit 11c, a PCIe interface (I / F) 11d, and a system bus 11e. In addition, a memory 14 is connected to the semiconductor integrated circuit 11.

[0028] The contro...

Example

[0055] (Second embodiment)

[0056] figure 2 It is a diagram showing an example of the information processing system of the second embodiment.

[0057] The information processing system 20 includes a plurality of semiconductor integrated circuits including semiconductor integrated circuits 21a0, 21a1, 21an, 21an+1, and a plurality of DRAMs including DRAM 22a0, 22a1, 22an, 22an+1. There are also two-stage switches 23 and 24.

[0058] The semiconductor integrated circuit 21a0 has a CPU 21b0, an ICU (Interrupt Controller Unit) 21c0, an MMU (Memory Management Unit) 21d0, a PCIe interface 21e0, and a system bus 21f0. In addition, the semiconductor integrated circuit 21a0 is connected to the DRAM 22a0.

[0059] CPU21b0 is figure 1 An example of the control circuit 11a shown controls each part of the semiconductor integrated circuit 21a0 via the system bus 21f0.

[0060] ICU21c0 is figure 1 The illustrated example of the interrupt control circuit 11b notifies the CPU 21b0 of the occurrence ...

Example

[0125] (Third embodiment)

[0126] Figure 8 It is a diagram showing an example of the information processing system of the third embodiment. in Figure 8 In, for and figure 2 The same elements of the information processing system 20 of the second embodiment shown are denoted by the same reference numerals. In the following, N semiconductor integrated circuits including semiconductor integrated circuits 41a0 to 41an+1 are referred to as SOC[0] to SOC[N]. For example, the semiconductor integrated circuit 41a0 is referred to as SOC[0], and the semiconductor integrated circuit 41a1 is referred to as SOC[1].

[0127] In the information processing system 40 of the third embodiment, two or more of SOC[0] to SOC[N] are connected to memories different from DRAM. in Figure 8 In the example, the memory 42a0 is connected to SOC[0], the memory 42an is connected to SOC[n], and the memory 42an+1 is connected to SOC[n+1].

[0128] The memories 42a0 to 42an+1 are information storage devices eac...

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PUM

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Abstract

The present invention increases the processing speed of an information processing system. A semiconductor integrated circuit (11) specifies, on the basis of memory map information (11m) that is defined by the address of the memories (14, 15) respectively used by semiconductor integrated circuits (11, 12), an address (a1) of a memory (15) connected to the semiconductor integrated circuit (12) thatis the destination for data transmission, converts the address (a1) to the address (a3) of the memory (15) that is defined in memory map information (12m) referenced by the destination for data transmission, and uses a PCIe interface (11d) to output the address (a3) and the transmission data, a switch (13) uses PCIe interfaces (13a, 13b) to transfer the address (a3) and the transmission data to the destination for data transmission, and the destination for data transmission uses a PCIe interface (12d) to receive the address (a3) and the transmission data and writes the transmission data into areception buffer region in the memory (15) corresponding to the address (a3).

Description

technical field [0001] The present invention relates to an information processing system, a semiconductor integrated circuit and an information processing method. Background technique [0002] As information processing systems become more complex and large-scale, information processing systems including a plurality of SoCs (System on Chip: System on Chip) have been proposed. As one of information processing systems including a plurality of SoCs, a CPU cluster in which a plurality of CPUs (Central Processing Units: central processing units) are connected via a network to realize parallel processing by each CPU has been proposed. [0003] In addition, conventionally, when connecting a plurality of servers using an Ethernet (registered trademark) switch, there is a technique of using PCIe (Peripheral Component Interconnect express: Peripheral Component Interconnect Express) in order to reduce the hardware of the Ethernet switch. Also, there is a technique in which a plurality ...

Claims

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Application Information

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IPC IPC(8): G06F13/38G06F13/36
CPCG06F13/4022Y02D10/00G06F13/42G06F13/36G06F13/38
Inventor 后藤诚司仁茂田永一冈本谕
Owner SOCIONEXT INC
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