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3d NAND flash memory and its preparation method

A flash memory and suppression layer technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of dielectric layer breakdown between adjacent gate layers, threshold voltage drift of gate layers, leakage of adjacent gate layers, etc. , to achieve the effect of reducing threshold voltage drift, reducing leakage, and reducing coupling effects

Active Publication Date: 2020-04-17
YANGTZE MEMORY TECH CO LTD
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  • Claims
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AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a 3D NAND flash memory and its preparation method, which is used to solve the problem that the 3D NAND flash memory in the prior art is easily caused by the reduction of the thickness of the inter-gate dielectric layer. Leakage between adjacent gate layers can even cause the breakdown of the inter-gate dielectric layer between adjacent gate layers. In 3D NAND flash memory, there is interlayer coupling interference between adjacent gate layers, resulting in gate The problem of threshold voltage drift of the gate layer, and the lateral loss of charge in the storage layer in 3D NAND flash memory, which causes the problem of threshold voltage drift of the gate layer

Method used

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  • 3d NAND flash memory and its preparation method
  • 3d NAND flash memory and its preparation method

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Embodiment 1

[0108] see figure 1 , the present invention provides a kind of preparation method of 3D NAND flash memory, the preparation method of described 3D NAND flash memory comprises steps:

[0109] 1) providing a semiconductor substrate, on which a stacked structure is formed, and the stacked structure includes alternately stacked sacrificial layers and insulating dielectric layers;

[0110]2) forming a channel via hole in the laminated structure, comprising the steps of: forming a vertical via hole in the laminated structure; removing part of the insulating dielectric layer by lateral etching based on the vertical via hole, forming a groove region between adjacent sacrificial layers and between the sacrificial layer and the semiconductor substrate;

[0111] 3) forming a functional sidewall on the surface of the sidewall of the channel through hole, and forming a channel layer on the surface of the functional sidewall and the bottom of the channel through hole; The portion between t...

Embodiment 2

[0189] see Figure 27 and Figure 28 , the present invention also provides a 3D NAND flash memory, the 3D NAND flash memory includes: a semiconductor substrate 10; a stacked structure 31, the stacked structure 31 is located on the semiconductor substrate 10, the stacked structure 10 includes Alternately stacked inter-gate dielectric layers 17 and gate layers 18, the inter-gate dielectric layer 17 includes alternately stacked first leakage suppression layers 171 and second leakage suppression layers 172; channel via holes 12, the channel The channel via hole 12 is located in the stacked structure 31; the channel via hole 12 includes a plurality of groove regions 122, and the groove region 122 is located between the adjacent gate layers 18 and the gate electrode Between the layer 18 and the semiconductor substrate 10; the functional sidewall 13, the functional sidewall 13 is located on the sidewall surface of the channel via hole 12, and the functional sidewall 13 is located ad...

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Abstract

The present invention provides a 3D NAND flash memory and its preparation method. 3D NAND flash memory includes: semiconductor substrate; stacked structure, located on the semiconductor substrate, the stacking structure includes alternately stacked grid medium layers and grid layers, grids, gridsThe intermediate medium layer includes the first leakage inhibitory layer and the second leakage inhibitory layer of the alternately stacked;Between the layers and the semiconductor substrate; the function of the function of the function, the side wall surface of the tug -of -hole hole, the function side wall is located between the adjacent grid polar layer and between the grid layer and the semiconductor substrateThe part is filled in the groove area; the channel layer is located in the channel of the channel, and the surface of the function side wall.The 3D NAND flash memory of the present invention can effectively reduce the leakage between the adjacent grid polar layers, improve the anti -breakdown capacity of the grille medium layer between the adjacent grid polar layers, and reduce the coupling effect between the adjacent grid polar layers.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a 3D NAND flash memory and a preparation method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) has been particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and it has high integration, fast access speed, easy erasing and resetting. It has the advantages of writing and so on, so it has been widely used in many fields such as microcomputer and automatic control. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] The stack structure of the existing 3D NAND flash memory is formed by alternately stacking multiple gate layers (ie gate word line layers) and i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157H01L27/11582
CPCH10B43/35H10B43/27
Inventor 肖莉红
Owner YANGTZE MEMORY TECH CO LTD
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