1results about How to "Addressing Threshold Voltage Drift" patented technology

This invention provides a voltage control method for erasing 3D NAND memory. When the bias voltage of the word line of a true memory cell is at the erase control voltage, the bias voltage of the well-doped region is raised to the erase working voltage and maintained. During the period when the bias voltage of the well-doped region rises to a first intermediate voltage, the bias voltage of the word line of the pseudo memory cell is maintained at a first preset voltage. Then, the word line of the pseudo memory cell is set to a floating state, wherein the first preset voltage is less than the first intermediate voltage. In this way, the voltage difference between the word line where the pseudo memory cell is located and the word line where the adjacent true memory cell is located is reduced, avoiding tunneling between the word line where the true memory cell is located and the word line where the pseudo memory cell is located, thereby avoiding threshold voltage drift of the pseudo memory cell, avoiding reduction of memory cell string current, and thus avoiding read errors of the true memory cell.