2results about How to "Addressing Threshold Voltage Drift" patented technology

This invention provides a voltage control method for erasing 3D NAND memory. When the bias voltage of the word line of a true memory cell is at the erase control voltage, the bias voltage of the well-doped region is raised to the erase working voltage and maintained. During the period when the bias voltage of the well-doped region rises to a first intermediate voltage, the bias voltage of the word line of the pseudo memory cell is maintained at a first preset voltage. Then, the word line of the pseudo memory cell is set to a floating state, wherein the first preset voltage is less than the first intermediate voltage. In this way, the voltage difference between the word line where the pseudo memory cell is located and the word line where the adjacent true memory cell is located is reduced, avoiding tunneling between the word line where the true memory cell is located and the word line where the pseudo memory cell is located, thereby avoiding threshold voltage drift of the pseudo memory cell, avoiding reduction of memory cell string current, and thus avoiding read errors of the true memory cell.

The application discloses a GOA circuit and a driving method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises a stage transmission module integrated with a stage transmission transistor. The drain of the stage transmission transistor is electrically connected with a first node. The source of the stage transmission transistor is electrically connected with a second node. The gate control end of an output module is electrically connected with the second node. The two side transmission ends of a potential control module are respectively electrically connected with the first node and a low potential line. The high potential end of the potential control module is electrically connected with a high potential line. The potential control module is used for transmitting the high potential signal of the high potential line to the first node in the stage transmission stage, so that the stage transmission transistor transmits the high potential signal to the output module through the second node. After the stage transmission is completed, the low potential signal of the low potential line is transmitted to the first node, so that the potential of the second node, to which the source of the stage transmission transistor is electrically connected, is continuously pulled down. The threshold voltage drift of the stage transmission transistor caused by voltage imbalance is eliminated, so that the display quality is improved.