44results about How to "Addressing Threshold Voltage Drift" patented technology

An embodiment of the invention discloses a shift register circuit and a driving method thereof, a gate drive circuit and a display device, and relates to the field of display. Stability characteristics of a GOA circuit can be improved without increasing the number of TFT in the GOA unit, and the problem that the stability characteristics and simple practicality cannot be obtained together is solved. The shift register circuit comprises a first-level shift register unit and a second-level shift register unit. The shift register circuit also comprises a stabilization module shared by the first-level shift register unit and the second-level shift register unit. The stabilization module is configured to stabilize electric potential of the output end of a pull-up node of the first-level shift register unit and the electric potential of the output end of a pull-up node of the second-level shift register unit when both the first-level shift register unit and the second-level shift register unit do not output effective signals.

The invention discloses a flexible display substrate as well a manufacturing method thereof and a flexible display device. The flexible display substrate comprises a flexible substrate; a thin film transistor and a light emitting device are formed above the flexible substrate; a light blocking layer is formed between the flexible substrate and the thin film transistor and used for blocking laser irradiating from one side of the flexible substrate. According to the technical scheme of the flexible display substrate as well the manufacturing method thereof and the flexible display device, as the light blocking layer is formed between the flexible substrate and the thin film transistor and capable of blocking laser irradiating from one side of the flexible substrate, damage to the thin film transistor caused by the light can be avoided, and therefore, the threshold voltage drift and the characteristics failure of the thin film transistor are avoided, and furthermore, the problems of display effect decline and even normal display failure of the flexible display substrate after laser stripping are avoided.

The invention provides a pixel circuit, a driving method of the pixel circuit and a display device with the pixel circuit. The pixel circuit comprises a first switch tube, a first capacitor, a second capacitor, a third capacitor, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube, wherein the source electrode of the first switch tube is connected with a data signal end; the gate electrode of the first switch tube is connected with a first control signal end; the first end of the first capacitor is connected with the drain electrode of the first switch tube; the first end of the second capacitor is connected with a second voltage signal end; the second end of the second capacitor is connected with that of the first capacitor; the first end of the third capacitor is connected with the first control signal end; the second end of the third capacitor is connected with the gate electrode of a driving tube; the source electrode of the second switch tube is connected with the gate electrode of the driving tube; the drain electrode of the second switch tube is connected with that of the driving tube; and the gate electrode of the second switch tube is connected with the first control signal end. The pixel circuit provided by the invention is used for compensating threshold voltage uniformity of the driving tube in the pixel circuit and solves the problem of poor luminance uniformity of an LED.

The invention provides a 3D NAND flash memory and a preparation method. The 3D NAND flash memory comprises a semiconductor substrate, a laminated structure, a channel through hole, a functional side wall and a channel layer, wherein the laminated structure is positioned on the semiconductor substrate, the laminated structure comprises inter-gate dielectric layers and grid layers which are superposed alternately; each inter-gate dielectric layer comprises first leakage inhibition layers and second leakage inhibition layers which are superposed alternately; the channel through hole is positionedinside the laminated structure; the functional side wall is positioned on the side wall surface of the channel through, the functional side wall comprises a plurality of separated storage units arranged along the depth direction of the channel through hole at intervals, and the storage units and the grid layers are arranged in a one-to-one correspondence mode; the channel layer is positioned inside the channel through hole, and is positioned on the surface of the functional side wall and the bottom of the channel through hole. According to the 3D NAND flash memory and the preparation method,electric leakage between adjacent grid layers can be reduced effectively, the breakdown resistance of the inter-gate dielectric layers between the adjacent grid layers is improved, and the coupling effect between the adjacent grid layers is reduced.

The invention provides an organic light-emitting diode pixel circuit, a driving method of the organic light-emitting diode pixel circuit and a display panel of the organic light-emitting diode pixel circuit. The organic light-emitting diode pixel circuit comprises an organic light-emitting diode, a first thin film transistor and a current conversion module. A grid of the first thin film transistor is connected with a line scan voltage signal, a source of the first thin film transistor is connected with a data voltage signal, and a drain of the first thin film transistor is connected with the current conversion module. The current conversion module is connected with a cathode of the organic light-emitting diode and a light-emitting control signal to be used for converting impressed voltage to drive current of the organic light-emitting diode. The organic light-emitting diode pixel circuit, the driving method of the organic light-emitting diode pixel circuit and the display panel of the organic light-emitting diode pixel circuit has the advantages of being capable of effectively solving the problems of drifting and inhomogeneity of threshold voltage which drives a thin film transistor and solving the IR Drop problem of rear panel power supply in the large-size active matrix or organic light-emitting diode (AMOLED) display so as to achieve uniformity of final display brightness.

The invention discloses a thin film transistor array substrate. In a thin film transistor of the array substrate, the material of an active layer is a metal oxide semiconductor material, an etching barrier layer is also arranged on the active layer, the etching barrier layer covers a channel region, and a light shielding layer is also arranged on the etching barrier layer. The method for preparing the abovementioned thin film transistor array substrate includes preparing and obtaining the etching barrier layer and the light shielding layer in a same photomask process. In addition, the invention also discloses a display device including the abovementioned thin film transistor array substrate. In the thin film transistor array substrate provided by the invention, through additional arrangement of the light shielding layer, influence of illumination on the active layer of the thin film transistor in a manufacture process is avoided, and the problems of threshold voltage drifting and electrical property failure of the thin film transistor due to illumination influence are prevented, thereby improving product quality.

A gate drive circuit comprises a plurality of gate drive units, comprising a pull-up control unit connected with a first node, a second node, a first clock signal, a scanning signal output end, a current-stage stage transmission signal output end and a preceding-stage transmission signal output end; a pull-down maintaining unit, connected with the first node, the second node, a current-stage feedback signal output end, a next-stage feedback signal output end, a scanning signal output end, a current-stage transmission signal output end, a first direct-current high voltage, a first direct-current low voltage and a second direct-current low voltage; a pull-up unit, connected with the first node, a second clock signal and a scanning signal output end; a downloading unit, connected with the first node, a second clock signal, a second direct-current high voltage, a local-stage feedback signal output end and a local-stage transmission signal output end; a pull-down unit, connected with the first node, the second node, the scanning signal output end, the next-stage cascade signal output end, the first direct-current low voltage and the second direct-current low voltage; and a bootstrap capacitor, one end of the bootstrap capacitor being connected with the first node, and the other end being connected with the scanning signal output end.

The invention discloses an organic glow display panel, a driving method and an organic glow display device thereof. The organic glow display panel comprises a plurality of pixel driving circuits. The pixel driving circuit comprises a first voltage terminal, a second voltage terminal, a scanning signal terminal, a data signal terminal, a first control signal terminal, a second control signal terminal, an electric potential collecting terminal, a driving module, an organic glow device, a brightness control module, a data writing module and an electric potential collecting module, wherein the driving module is utilized to drive the organic glow device to glow under the control of the control terminal and based on the voltage supplied by the first voltage terminal; the brightness control module is utilized to control the brightness of the organic glow device by controlling the first end of the driving module and the electric potential of the control terminal; the data writing module is utilized to write the signal of the data signal terminal into the control terminal of the driving module under the control of the scanning signal terminal. The organic glow display panel and the organic glow display device have the advantage of being capable of avoiding the drift of threshold voltage.

The invention belongs to the technical field of semiconductors, and discloses a planar split dual-gate thin film transistor and a preparation method thereof. The method comprises the following steps: (1) depositing insulating medium materials on a substrate to serve as a transition layer; (2) depositing a conduction thin film on the transition layer, and carrying out photoetching to form two gate electrodes; (3) depositing insulation thin films on the transition layer and the gate electrodes to form an insulated gate medium layer; (4) depositing a thin film on the insulated gate medium layer to form a semiconductor active layer; (5) spinning a photoresist layer on the semiconductor active layer, and carrying out photoetching to form the contact hole of a source / drain electrode; (6) depositing the conduction thin film on the contact hole and the photoresist, and stripping to form the source electrode and the drain electrode; and (7) carrying out annealing processing. The bias voltages of two gate electrodes are regulated to cause a TFT (Thin Film Transistor) device to present different output and transfer characteristics, the two gate electrodes can be simultaneously used as a control gate and a signal gate, a circuit is simplified, and the application range of the TFT is effectively expanded.

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate, wherein at least one first thin film transistor and at least one second thin film transistorare positioned on one side of the substrate; an active layer of the first thin film transistor is low-temperature polycrystalline silicon, and an active layer of the second thin film transistor is anoxide semiconductor; a gate electrode of the second thin film transistor comprises a top gate electrode and a bottom gate electrode, and the top gate electrode and the bottom gate electrode are connected through a via hole; the gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor are located on different layers; and a source electrode and a drainelectrode of the first thin film transistor, a source electrode and a drain electrode of the second thin film transistor and the top gate electrode are located on the same layer. According to the array substrate provided by the embodiment of the invention, the stability of the electrical property of a driving circuit on the array substrate is improved through the second thin film transistor withthe double-gate structure.

The invention provides a 3D NAND flash memory and a fabrication method thereof. The fabrication method comprises the following steps of providing a semiconductor substrate, wherein a lamination structure is formed on the semiconductor substrate and comprises sacrifice layers and gate layers which are alternatively laminated; forming a channel through hole in the lamination structure, wherein the channel through hole comprises a plurality of groove regions, and the groove regions are arranged between adjacent gate layers and between the gate layer and the semiconductor substrate; forming a functional side wall on a surface of a side wall of the channel through hole, and forming channel layers on a surface of the functional side wall and at the bottom of the channel through hole; forming a gate gap in the lamination structure; removing the sacrifice layers according to the gate gap; and forming gate dielectric layers between adjacent gate layers and between the gate layer and the semiconductor substrate, wherein each gate dielectric layer comprises first electric leakage suppression layers and second electric leakage suppression layers which are alternatively laminated. By the fabrication method, electric leakage between adjacent gate layers can be effectively reduced, the breakdown-resistant capability of the gate dielectric layer between adjacent gate layers is improved, and the coupling effect between adjacent gate layers is reduced.

The invention provides a voltage control method during erasing of a 3D NAND memory. When the bias voltage of the word line of the true memory cell is at the erase control voltage; raising the bias voltage of the well doped region to an erase working voltage and keeping the erase working voltage; when the bias voltage of the well doped region rises to a first intermediate voltage, the well doped region is grounded; keeping the bias voltage of the word line of the pseudo memory cell at a first preset voltage, then, setting a word line of the pseudo memory unit to be in a floating state; whereinthe first preset voltage is smaller than the first intermediate voltage; thus, the voltage difference between the voltage of the word line where the pseudo memory cell is located and the voltage of the word line where the adjacent true memory cell is located is reduced; tunneling between the word line where the true memory unit is located and the word line where the pseudo memory unit is located is avoided, so that threshold voltage drift of the pseudo memory unit is avoided, reduction of string current of the memory unit is avoided, and reading errors of the true memory unit are avoided.

The invention discloses a gate scanning circuit and a display panel. The gate scanning circuit comprises N shift registers arranged sequentially in the first direction, wherein N is a positive integer more than 4; the shift register has a first scanning sequence control end, a second scanning sequence control end, a first input end, a second input end and an output end; the N shift registers are sequentially a first-stage shift register to an N-stage shift register in the first direction; for the n-stage shift register, the first scanning sequence control end is connected with the output end of the n-c-stage shift register, the second scanning sequence control end is connected with the output end of the n+d-stage shift register, the first input end is connected with the output end of the n-a-stage shift register, and the second input end is connected with the output end of the n+b-stage shift register. The technical solution solves the problem of direct current bias of the gate scanning circuit, and improves the stability and the reliability.

The invention provides a pixel drive circuit, a display device and a pixel drive method. The pixel drive circuit comprises a signal line, a control line, a power unit and a drive unit, and further comprises a compensation unit, wherein the signal line, the control line, the power unit and the drive unit are connected with the compensation unit. The power unit is used for supplying power to a light-emitting element. The drive unit is used for driving the light-emitting element. The signal line is used for providing a data signal for the compensation unit. The control line is used for providing a control signal for the compensation unit. The compensation unit is used for conducting threshold voltage compensation on the drive unit according to the data signal and the control signal. The pixel drive circuit prevents working current of the drive unit from being influenced by the threshold voltage of the drive unit due to the arrangement of the compensation unit, and therefore the influences of the threshold voltage of the drive circuit on the working current of the drive unit are eliminated, the problem of threshold voltage drifting which is caused by the process manufacture procedure and long-time operation to the drive unit is thoroughly solved, and it is ensured that the display luminance of the light-emitting element is uniform.

The invention provides a polysilicon thin film transistor and a manufacturing method thereof. The manufacturing method comprises the steps of: providing a substrate, forming a polysilicon active layeron the substrate, sequentially forming a gate insulating layer and a polysilicon gate layer on the polysilicon active layer; performing a chemico-mechanical polishing process for removing a part of asidewall covering layer above the polysilicon gate layer; and performing a first ion implantation process to implant ions into the polysilicon gate layer; performing a second ion implantation processto implant ions into the polysilicon gate layer and polysilicon active layer on both sides of the sidewall, so as to form a source doped region and a drain doped region. Under the condition that theion implantation dose of the polysilicon gate layer is not reduced, the source-drain depletion region overlap is reduced by reducing the ion implantation doses of the source doped region and the draindoped region, thereby preventing source and drain penetration. At the same time, the ion implantation dose of the polysilicon gate layer is ensured, the threshold voltage drift of the thin film transistor is avoided, and the characteristics of the polysilicon thin film transistor are improved.

The invention provides a low-temperature polycrystalline silicon thin film manufacturing method, a low-temperature polycrystalline silicon thin film and related devices and belongs to the field of display panel manufacturing. The low-temperature polycrystalline silicon thin film manufacturing method comprises the following steps: forming an amorphous silicon layer on a substrate; forming an alkali metal ion adsorption layer on the amorphous silicon layer; conducting quasi-molecular laser annealing on the substrate on which the alkali metal ion adsorption layer is formed to convert the amorphous silicon layer into a polycrystalline silicon layer; removing the alkali metal ion adsorption layer to form a polycrystalline silicon thin film on the substrate. According to the technical scheme provided by the invention, alkali metal ions in the low-temperature polycrystalline silicon thin film can be reduced, so that the threshold voltage drift of a low-temperature polycrystalline silicon thin film transistor is effectively prevented.

The invention provides a 3D NAND flash memory and a method of fabricating the same. The 3D NAND flash memory comprises the following parts of a semiconductor substrate; a stacked structure on the semiconductor substrate and comprising alternately stacked inter-gate dielectric layers and gate layers, wherein the inter-gate dielectric layers comprise alternately stacked first leakage suppression layer and second leakage suppression layer; a channel via hole located in the stacked structure and comprising a plurality of groove regions that are located between adjacent gate layers and between thegate layers and the semiconductor substrate; functional sidewalls disposed on the sidewall surface of the channel via hole, wherein the portion of the functional sidewalls between adjacent gate layersand between the gate layers and the semiconductor substrate is filled in the groove regions; and a channel layer located in the channel via hole and on the surface of the functional sidewalls. The 3DNAND flash memory provided by the invention can effectively reduce the leakage between adjacent gate layers, improve the anti-breakdown capability of the inter-gate dielectric layers between adjacentgate layers, and reduce the coupling effect between adjacent gate layers.

The invention discloses an array substrate row driving circuit and a display device. An array substrate row driving unit in the array substrate row driving circuit comprises a plurality of thin film transistors, and each thin film transistor comprises a substrate, an active layer, a gate insulating layer, a gate, a first insulating layer, a source and a drain; the gate insulating layer is positioned on the active layer and covers the middle region of the active layer; the gate is located on the gate insulating layer, the vertical projection of the gate on the substrate coincides with the vertical projection of a channel region on the substrate, the first insulating layer is located on the substrate, the active layer, the gate insulating layer and the gate, the source and the drain are located on the first insulating layer, the source is electrically connected with the source region, and the drain is electrically connected with the drain region. According to the technical scheme provided by the embodiment of the invention, the problem of threshold voltage drift of the thin film transistor is solved, the stability of the array substrate row driving circuit is improved, and normal display of the display device is ensured.

The embodiment of the invention discloses a pixel driving circuit and a display panel. The pixel driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a first capacitor, a second capacitor, and a light-emitting device, wherein the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are connected to a first scanning line, a second scanning line, a third scanning line, a data signal line, a reset signal line and a control signal line respectively. The pixel driving circuit can effectively compensate the threshold voltage of the driving thin film transistor, solves the problem that the current flowing through the light-emitting device is unstable due to threshold voltage drift, enables the light-emitting brightness of the light-emitting device to be uniform, and improves the display effect of a picture.

Disclosed are a thin film transistor array panel and a liquid crystal display (LCD) device. The thin film transistor array panel comprises a plurality of gate lines, data lines, a plurality of pixel units and a multistage gate driving signal generation unit, wherein the plurality of gate lines and the data lines are perpendicular to each other. Each pixel unit comprises at least one thin film transistor, the gate lines are connected with a grid electrode of the thin film transistor, and the data lines are connected with a source electrode of the thin film transistor. The multistage gate driving signal generation unit is connected with the gate lines and is used for receiving a first grid driving control signal, a second grid driving control signal, a gate source signal and a negative voltage signal and supplying gate driving signals to the gate lines. The phase position of the first grid driving control signal is opposite to the phase position of the second grid driving control signal. By means of the thin film transistor array panel and the LCD device, a narrow frame of the thin film transistor array panel can be achieved.

The present invention provides a manufacturing method of an array substrate and a manufacturing method of a display device. According to the invention, when an isolation layer is manufactured, an isolation column is manufactured at the same time. The method specifically comprises the following steps of S1, forming an isolation layer, wherein the film of the isolation layer is made of organic materials; S2, patterning the film of the isolation layer to form a desired pattern and an isolation part of the isolation layer; S3, subjecting the isolation part to high-temperature treatment to increase the thickness of the isolation part and form an isolation column. According to the manufacturing method of the array substrate, not only the production period can be shortened, but also the production cost is reduced. Meanwhile, the generation of threshold voltage drift of a TFT due to the large-area ultraviolet irradiation can be avoided.

Provided is a gate driving circuit comprising: a plurality of gate driving units 1, comprising: a pull-up control unit 200, which is connected to a first and a second nodes Q and N, a first clock signal CK1, a scan signal output terminal G(n), a current stage transmission signal output terminal Cout(n) and a previous stage transmission signal output terminal Cout(n-1); a pull-down maintenance unit 500, which is connected to the first and second nodes Q and N, a current stage feedback signal output terminal Out(n), a next stage feedback signal output terminal Out(n+1), the scan signal output terminal G(n), the current stage transmission signal output terminal Cout(n), a first DC high voltage VGH1, a first and second DC low voltages VGL1 and VGL2; a pull-up unit 100, which is connected to the first node Q, the second clock signal and the scan signal output terminal; a downstream unit 400, which is connected to the first node Q, the second clock signal CK2, a second DC high voltage VGH2, the current stage feedback signal output terminal Out(n), and the current stage transmission signal output terminal Cout(n); a pull-down unit 300, which is connected to the first and second nodes Q and N, the scan signal output terminal G(n), the next stage transmission signal output terminal Out(n+1), and the first and second DC low voltages VGL1 and VGL2; a bootstrap capacitor Cbt, one end of the bootstrap capacitor Cbt is connected to the first node Q, and the other end is connected to the scan signal output terminal G(n).

The invention discloses a flexible display substrate, a manufacturing method thereof, and a flexible display device. The flexible display substrate includes: a flexible substrate, a thin film transistor and a light emitting device are formed on the flexible substrate, a light blocking layer is formed between the flexible substrate and the thin film transistor, and the light blocking layer is used to block the Laser light irradiated on one side of the flexible substrate. In the flexible display substrate and its manufacturing method and the technical solution of the flexible display device provided by the present invention, a light-blocking layer is formed between the flexible substrate and the thin film transistor, and the light-blocking layer can block the laser light irradiated from the side of the flexible substrate, avoiding the The laser causes damage to the thin film transistor, thereby avoiding the threshold voltage drift of the thin film transistor and the failure of the characteristics of the thin film transistor, thereby avoiding the problem that the display effect of the flexible display substrate decreases or even cannot be displayed normally after laser stripping.