3D NAND flash memory and method of fabricating the same

Abstract

The invention provides a 3D NAND flash memory and a method of fabricating the same. The 3D NAND flash memory comprises the following parts of a semiconductor substrate; a stacked structure on the semiconductor substrate and comprising alternately stacked inter-gate dielectric layers and gate layers, wherein the inter-gate dielectric layers comprise alternately stacked first leakage suppression layer and second leakage suppression layer; a channel via hole located in the stacked structure and comprising a plurality of groove regions that are located between adjacent gate layers and between thegate layers and the semiconductor substrate; functional sidewalls disposed on the sidewall surface of the channel via hole, wherein the portion of the functional sidewalls between adjacent gate layersand between the gate layers and the semiconductor substrate is filled in the groove regions; and a channel layer located in the channel via hole and on the surface of the functional sidewalls. The 3DNAND flash memory provided by the invention can effectively reduce the leakage between adjacent gate layers, improve the anti-breakdown capability of the inter-gate dielectric layers between adjacentgate layers, and reduce the coupling effect between adjacent gate layers.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a 3D NAND flash memory and a preparation method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) has been particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and it has high integration, fast access speed, easy erasing and resetting. It has the advantages of writing and so on, so it has been widely used in many fields such as microcomputer and automatic control. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] The stack structure of the existing 3D NAND flash memory is formed by alternately stacking multiple gate layers (ie gate word line layers) and i...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a 3D NAND flash memory and its preparation method, which is used to solve the problem that the 3D NAND flash memory in the prior art is easily caused by the reduction of the thickness of the inter-gate dielectric layer. Leakage between adjacent gate layers can even cause the breakdown of the inter-gate dielectric layer between adjacent gate layers. In 3D NAND flash memory, there is interlayer coupling interference between adjacent gate layers, resulting in gate The problem of threshold voltage drift of the gate layer, and the lateral loss of charge in the storage layer in 3D NAND flash memory, which causes the problem of threshold voltage drift of the gate layer

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