Array substrate row driving circuit and display device

A technology for array substrate rows and driving circuits, which is applied in circuits, electrical components, electrical solid devices, etc., and can solve problems such as threshold voltage drift of thin film transistors

Active Publication Date: 2020-04-28
GUANG ZHOU NEW VISION OPTO ELECTRONICS TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The invention provides an array substrate row driving circuit and a display device to solve the threshold voltage drift problem of t

Method used

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  • Array substrate row driving circuit and display device
  • Array substrate row driving circuit and display device
  • Array substrate row driving circuit and display device

Examples

Experimental program
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Effect test

example 1

[0091] Five thin film transistors with lengths L1, L2, L3, L4, and L5 forming the first lightly doped region and the second lightly doped region respectively have a width-to-length ratio of 10:5 μm, where L1=1.5um, L2=1.0um, L3=0.5um, L4=0.1um, L5=0um. In particular, L5=0um can also correspond to a reference device without an offset feature.

[0092] The specific method of forming the above five thin film transistors is as follows:

[0093] A whole layer of active layer is formed on the base substrate, the main material of the whole layer of active layer is oxide semiconductor, the dopant material is tantalum, and the thickness is 20nm, and then the whole layer of active layer is patterned to obtain the active layer. layer;

[0094] The entire gate insulating layer is formed on the active layer by PECVD process, and the entire gate insulating layer is a single layer of SiO 2Thin film, the thickness is 300nm, the deposition temperature is 230℃, the gas and gas ratio used are...

example 2

[0103] Five thin-film transistors with lengths L6, L7, L8, L9, and L10 forming the first lightly doped region and the second lightly doped region respectively have an aspect ratio of 10:5 μm, where L6=1.5um, L7=1.0um, L8=0.5um, L9=0.1um, L10=0um. In particular, L10=0um can also correspond to a reference device without an offset feature.

[0104] The specific method of forming the above five thin film transistors is as follows:

[0105] A whole layer of active layer is formed on the base substrate, the main material of the whole layer of active layer is oxide semiconductor, the dopant material is praseodymium, and the thickness is 20nm, and then the whole layer of active layer is patterned to obtain the active layer. layer;

[0106] The entire gate insulating layer is formed on the active layer by PECVD process, and the entire gate insulating layer is a single layer of SiO 2 Thin film, the thickness is 300nm, the deposition temperature is 230℃, the gas and gas ratio used are...

example 3

[0115] Five thin film transistors with lengths L11, L12, L13, L14, and L15 forming the first lightly doped region and the second lightly doped region respectively have an aspect ratio of 10:5 μm, where L11=1.5um, L12=1.0um, L13=0.5um, L14=0.1um, L15=0um. In particular, L15=0um can also correspond to a reference device without an offset feature.

[0116] The specific method of forming the above five thin film transistors is as follows:

[0117] The entire active layer is formed on the base substrate, the main material of the entire active layer is oxide semiconductor, the doping material is ytterbium, and the thickness is 30nm, and then the entire active layer is patterned to obtain the active layer. layer;

[0118] The entire gate insulating layer is formed on the active layer by PECVD process, and the entire gate insulating layer is a single layer of SiO 2 Thin film, the thickness is 300nm, the deposition temperature is 250℃, the gas and gas ratio used are SiH 4 / N 2 O / A...

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Abstract

The invention discloses an array substrate row driving circuit and a display device. An array substrate row driving unit in the array substrate row driving circuit comprises a plurality of thin film transistors, and each thin film transistor comprises a substrate, an active layer, a gate insulating layer, a gate, a first insulating layer, a source and a drain; the gate insulating layer is positioned on the active layer and covers the middle region of the active layer; the gate is located on the gate insulating layer, the vertical projection of the gate on the substrate coincides with the vertical projection of a channel region on the substrate, the first insulating layer is located on the substrate, the active layer, the gate insulating layer and the gate, the source and the drain are located on the first insulating layer, the source is electrically connected with the source region, and the drain is electrically connected with the drain region. According to the technical scheme provided by the embodiment of the invention, the problem of threshold voltage drift of the thin film transistor is solved, the stability of the array substrate row driving circuit is improved, and normal display of the display device is ensured.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of driving circuits, and in particular, to an array substrate row driving circuit and a display device. Background technique [0002] The array substrate row driving technology realizes the preparation of the row driving circuit on the substrate substrate in the non-display area, thereby simplifying the preparation process of the display panel, effectively reducing the production cost of the display panel, improving the integration degree of the display panel, and further It is beneficial to narrow the frame of the display panel. [0003] The array substrate row driving circuit includes a plurality of cascaded array substrate row driving units, and the array substrate row driving unit includes a plurality of thin film transistors. In the prior art, thin film transistors are formed by the preparation process of oxide thin film transistors. The oxide substrate has the advantages of high ...

Claims

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Application Information

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IPC IPC(8): H01L27/12H01L29/423H01L29/786H01L21/34
CPCH01L27/1225H01L27/1255H01L29/78696H01L29/7869H01L29/42364H01L29/42384H01L29/66969H01L2029/42388
Inventor 周雷陶洪徐苗李民
Owner GUANG ZHOU NEW VISION OPTO ELECTRONICS TECH
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