3d NAND flash memory and its preparation method

Abstract

The invention provides a 3D NAND flash memory and a preparation method thereof, comprising the following steps: providing a semiconductor substrate, on which a stacked structure is formed, including alternately stacked sacrificial layers and gate layers; forming a trench in the stacked structure The channel via hole; the channel via hole includes several groove regions between adjacent gate layers and between the gate layer and the semiconductor substrate; the functional sidewall is formed on the side wall surface of the channel via hole, and The surface of the functional sidewall and the bottom of the channel via hole form a channel layer; form a gate gap in the stack structure; remove the sacrificial layer based on the gate gap; between adjacent gate layers and between the gate layer and the semiconductor substrate An inter-gate dielectric layer is formed between the bottom, and the inter-gate dielectric layer includes alternately stacked first leakage suppression layers and second leakage suppression layers. The invention can effectively reduce the electric leakage between the adjacent gate layers, improve the breakdown resistance of the inter-gate dielectric layer between the adjacent gate layers, and reduce the coupling effect between the adjacent gate layers.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a 3D NAND flash memory and a preparation method. Background technique [0002] In recent years, the development of flash memory (Flash Memory) has been particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and it has high integration, fast access speed, easy erasing and resetting. It has the advantages of writing and so on, so it has been widely used in many fields such as microcomputer and automatic control. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] The stack structure of the existing 3D NAND flash memory is formed by alternately stacking multiple gate layers (ie gate word line layers) and inter-gat...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a 3D NAND flash memory and its preparation method, which are used to solve the problem that the 3D NAND flash memory in the prior art is easily caused by the reduction of the thickness of the inter-gate dielectric layer. Leakage between gate layers may even cause the breakdown of the inter-gate dielectric layer between adjacent gate layers. In 3D NAND flash memory, inter-layer coupling interference between adjacent gate layers may cause gate layer The problem of threshold voltage drift in 3D NAND flash memory, and the lateral loss of charge in the storage layer in 3D NAND flash memory, resulting in the problem of threshold voltage drift of the gate layer

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