3D NAND flash memory and fabrication method thereof

Abstract

The invention provides a 3D NAND flash memory and a fabrication method thereof. The fabrication method comprises the following steps of providing a semiconductor substrate, wherein a lamination structure is formed on the semiconductor substrate and comprises sacrifice layers and gate layers which are alternatively laminated; forming a channel through hole in the lamination structure, wherein the channel through hole comprises a plurality of groove regions, and the groove regions are arranged between adjacent gate layers and between the gate layer and the semiconductor substrate; forming a functional side wall on a surface of a side wall of the channel through hole, and forming channel layers on a surface of the functional side wall and at the bottom of the channel through hole; forming a gate gap in the lamination structure; removing the sacrifice layers according to the gate gap; and forming gate dielectric layers between adjacent gate layers and between the gate layer and the semiconductor substrate, wherein each gate dielectric layer comprises first electric leakage suppression layers and second electric leakage suppression layers which are alternatively laminated. By the fabrication method, electric leakage between adjacent gate layers can be effectively reduced, the breakdown-resistant capability of the gate dielectric layer between adjacent gate layers is improved, and the coupling effect between adjacent gate layers is reduced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a 3D NAND flash memory and a preparation method. Background technique [0002] In recent years, the development of flash memory (Flash Memory) has been particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and it has high integration, fast access speed, easy erasing and resetting. It has the advantages of writing and so on, so it has been widely used in many fields such as microcomputer and automatic control. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] The stack structure of the existing 3D NAND flash memory is formed by alternately stacking multiple gate layers (ie gate word line layers) and inter-gat...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a 3D NAND flash memory and its preparation method, which are used to solve the problem that the 3D NAND flash memory in the prior art is easily caused by the reduction of the thickness of the inter-gate dielectric layer. Leakage between gate layers may even cause the breakdown of the inter-gate dielectric layer between adjacent gate layers. In 3D NAND flash memory, inter-layer coupling interference between adjacent gate layers may cause gate layer The problem of threshold voltage drift in 3D NAND flash memory, and the lateral loss of charge in the storage layer in 3D NAND flash memory, resulting in the problem of threshold voltage drift of the gate layer

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