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Use double -sided logical circuit block layout

A technology of integrated circuits and transistors, applied in the field of logic circuit block layout

Active Publication Date: 2021-03-26
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, these FEOL processes are usually limited to the formation of CMOS transistors on one side of the semiconductor wafer

Method used

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  • Use double -sided logical circuit block layout
  • Use double -sided logical circuit block layout
  • Use double -sided logical circuit block layout

Examples

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Embodiment Construction

[0028] The detailed description set forth below with respect to the accompanying figures is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. As described herein, the use of the term "and / or" is intended to mean an "inclusive or", and the use of the term "or" is intended to mean an "exclusive or".

[0029] Due to cost and power consumption considerations, mobile radio frequency (RF) chip designs (eg, mobile RF transceivers) have migrated to deep sub-micron process nodes. The design comp...

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Abstract

An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer (620). The integrated circuit device may also include n-type metal oxide semiconductor (NMOS) transistors supported by the front side of the isolation layer opposite the back side. The integrated circuit device may further include a shared contact (640) extending through the isolation layer and electrically coupling the first terminal of the PMOS transistor to the first terminal of the NMOS transistor.

Description

technical field [0001] The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to logic circuit block layout utilizing double-sided processing. Background technique [0002] Due to cost and power consumption considerations, mobile radio frequency (RF) chip designs (eg, mobile RF transceivers) that include high performance duplexers have migrated to deep sub-micron process nodes. The design of such mobile RF transceivers becomes complex at this deep submicron process node. The design complexity of these mobile RF transceivers is further complicated by the added circuit functionality to support communication enhancements such as carrier aggregation. Further design challenges for mobile RF transceivers include analog / RF performance considerations such as mismatch, noise and other performance considerations. The design of these mobile RF transceivers includes the use of additional passive components, for example...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/822H01L21/768H01L21/8238H01L27/06H01L27/092
CPCH01L21/76895H01L21/8221H01L27/0694H01L27/092H01L21/84H01L21/845H01L27/1203H01L27/1211H01L21/76897H01L23/481H01L23/485H01L21/823871H01L2224/11H01L21/76898H01L21/823821H01L21/823878H01L27/0924H01L29/0649H01L29/0676H01L29/42392
Inventor S·格科特佩里J·理乔德
Owner QUALCOMM INC