High-k dielectric layer and method for forming same in three-dimensional memory device

Abstract

Embodiments of 3D memory devices having one or more high-k dielectric layers and methods of forming the same are disclosed. In an example, a 3D memory device includes: a substrate; a memory stack including a high-k dielectric layer over the substrate and a plurality of interleaved conductor and dielectric layers over the high-k dielectric layer; and a semiconductor plug disposed over the substrate and in the opening of the high-k dielectric layer.

Description

Background technique [0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of fabricating the same, and in particular, to high-k dielectric layers in 3D memory devices and methods of fabricating the same. [0002] By improving process technology, circuit design, programming algorithms, and manufacturing processes, planar memory cells are being scaled to smaller sizes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of planar memory cells is approaching an upper limit. [0003] 3D memory architectures can address the density constraints in planar memory cells. A 3D memory architecture includes a memory array and peripherals for controlling signals to and from the memory array. It has the advantage of taking up less wafer area than planar memory cells of the same bit density. Memory strings in a 3D memory ...

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Problems solved by technology

[0004] However, as cell sizes continue to shrink, various issues have arisen in terms of cost, reliability, and performance of existing 3D memory structures and fabrication methods

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