Driving control circuit, driving control chip, integrated packaging device, display system and sparse driving method
A technology for driving control circuits and circuits, which is applied in the direction of electrical components, instruments, electric light sources, etc., can solve problems such as increased costs, difficult wiring, and large driver chips, and achieves the effect of increasing the refresh frame rate and reducing the bandwidth required for work
Active Publication Date: 2019-08-30
FAITH BILLION TECH DEV LTD
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Problems solved by technology
Although the static scanning driver can meet the requirements of light field display technology, the driver chip it needs is too large and the wiring is difficult, which greatly increases the cost
Method used
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Embodiment
[0064] refer to figure 1 , figure 1 A schematic diagram of the circuit structure of a drive control circuit provided by an embodiment of the present invention, the drive control circuit includes a data input terminal SDI, a clock input terminal DCLK, a decoding and control unit 101, M decoding gating units 102, N+1 driving sources 103 and N+1 driving signal output terminals (OUT0, OUT1, ... OUTN); for example, the number of M can be an integer between 1 and 4, and N can be an integer between 0 and 111 .
[0065] The decoding and control unit 101 includes a first input terminal C1, a second input terminal C2, at least two control output terminals (C3, C5) and at least two address output terminals (C4, C6), and at least two control output terminals ( C3, C5) are in one-to-one correspondence with at least two address output terminals (C4, C6); the first input terminal C1 of the decoding and control unit 101 is electrically connected with the data input terminal SDI, and the sec...
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The invention discloses a driving control circuit, a driving control chip, an integrated packaging device, a display system and a sparse driving method. The driving control circuit includes a data input end, a clock input end, a decoding and control unit, at least two decoding gating units, at least two driving sources and at least two driving signal output ends, wherein a first input end of the decoding and control unit is electrically connected with the data input end, a second input end is electrically connected with the clock input end, a control input end of each decoding gating unit is electrically connected with a corresponding control output end, an address input end is electrically connected with a corresponding address output end, the at least two output ends are in one-to-one correspondence electrical connection with first ends of the at least two driving sources, and second ends of the at least two driving sources are in one-to-one correspondence electrical connection withthe at least two driving signal output ends. The driving control circuit is advantaged in that data inputted by the data input end aree directly inputted to the corresponding decoding gating units, output of the driving signal output ends is controlled by the decoding gating units, when the bandwidth is constant, the maximum refresh frame rate is greatly improved.
Description
technical field [0001] Embodiments of the present invention relate to drive control technology, and in particular to a drive control circuit, a drive control chip, an integrated packaging device, a display system, and a sparse drive method. Background technique [0002] With the application of light field display technology and dense display devices more and more widely, however, because light field display technology requires a higher refresh frame rate of driving technology, how to drive dense display devices to form light field display is becoming more and more difficult. be valued. [0003] The traditional drive methods include passive address selection drive, active address selection drive and dynamic scanning drive, etc. The refresh frame rate is low. For example, the refresh frame rate of passive address selection drive and active address selection drive is generally 60Hz to 120Hz , the refresh frame rate driven by dynamic scanning can reach 3.8KHz, and in some cases...
Claims
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IPC IPC(8): H05B33/08G09G3/32H05B44/00
CPCG09G3/32H05B45/10G09G2310/0275G09G2370/08G09G2350/00G09G2340/0435G09G2310/08G09G2354/00G09G3/002G09G3/003G09G3/2088G09G2310/0297H01L25/0753H01L33/0093G09G3/005H04N13/307G02B30/33Y02B20/40G06F3/013G09G2310/0291
Inventor 卢增祥
Owner FAITH BILLION TECH DEV LTD