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Package structure

A technology of packaging structure and circuit structure, applied in semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of inability to control the contact density, complex process, high cost, etc., and achieve the effect of increasing the signal transmission space of the chip

Active Publication Date: 2021-07-16
UNIMICRON TECH CORP
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  • Abstract
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Problems solved by technology

However, the volume and thickness of the silicon interposer are large, which also causes problems such as high cost and complicated process.
[0003] Embedded multi-die interconnect bridge technology (embedded multi-die interconnect bridge, EMIB) uses embedded chips as a bridge structure. However, when chips are connected using a flip-chip process, the density of conductive contacts will still be affected due to the fact that the substrate is a flat surface. However, it is limited, and cannot have a greater control over the contact density

Method used

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Embodiment Construction

[0026] A number of implementations of the present invention will be disclosed below with the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known and commonly used structures and components will be shown in a simple and schematic manner in the drawings. And for clarity, the thicknesses of layers and regions in the drawings may be exaggerated, and the same component symbols denote the same components in the description of the drawings.

[0027] Figure 1A to Figure 1C It is a cross-sectional view of different stages of manufacturing the encapsulation structure 100a in an embodiment of the present invention. see Figure 1A , the first...

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Abstract

The invention discloses a packaging structure, which includes a first substrate, a second substrate, a plurality of chips, a plurality of first conductive elements and a plurality of second conductive elements. The first substrate has a recessed area, and the second substrate is disposed in the recessed area and protrudes from the first substrate. The chip is arranged on the first substrate and the second substrate, so that the second substrate is located between the first substrate and the chip. The first conductive element is located between the chip and the first substrate, and the chip is electrically connected to the first substrate through the first conductive element. The second conductive element is located between the plurality of chips and the second substrate, and the chips are electrically connected to the second substrate through the second conductive element. Therefore, under the same packaging structure area and volume, the purpose of increasing the signal transmission space of the chip passing through the second substrate can be achieved, and at the same time, the length of the circuit can be shortened to improve the transmission efficiency.

Description

technical field [0001] The invention relates to a packaging structure, in particular to a packaging structure which increases the signal transmission space of a chip. Background technique [0002] In today's packaging process, many methods have been proposed in order to provide a higher density of chip connection points. For example, a silicon interposer (Silicon interposer) is placed between the chip and the substrate, and is electrically connected by the through-silicon via technology. However, the volume and thickness of the silicon interposer are large, which also causes problems such as high cost and complicated process. [0003] Embedded multi-die interconnect bridge technology (embedded multi-die interconnect bridge, EMIB) uses embedded chips as a bridge structure. However, when chips are connected using a flip-chip process, the density of conductive contacts will still be affected due to the fact that the substrate is a flat surface. However, it is limited, and it ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/065H01L23/498
CPCH01L23/49822H01L23/49827H01L23/49838H01L25/0655H01L2224/16225H01L2924/15151
Inventor 林义邱俊铭李鸿志陈昌甫
Owner UNIMICRON TECH CORP