Pulse-width modulation controller and tri-state voltage generation method

Abstract

A pulse-width modulation (PWM) controller including an output pin, a temporary voltage generation circuit and a tri-state voltage generation circuit is disclosed. The temporary voltage generation circuit includes a voltage-dividing unit and a control unit. The voltage-dividing unit is coupled to the output pin and the control unit respectively. The control unit receives an enable signal and a PWM signal. The tri-state voltage generation circuit is coupled to the temporary voltage generation circuit and the output pin and receives the enable signal, the PWM signal and a tri-state input voltage. When the PWM controller is operated in a tri-state mode, the control unit controls the voltage-dividing unit to provide a temporary voltage to the output pin according to the enable signal and PWM signal, and then the tri-state voltage generation circuit provides a tri-state voltage to the output pin according to the enable signal and PWM signal.

Description

technical field [0001] The present invention relates to a power supply circuit, in particular to a pulse width modulation controller and a method for generating a third-state voltage. Background technique [0002] In the operation of the existing power supply circuit, in order to reduce the switching energy loss, there will be a period of time when the zero current (ZeroCurrent, ZC) controls both the upper bridge switch and the lower bridge switch to be non-conductive. At this time, the PWM signal has a voltage level between a high voltage level (High-level) and a low voltage level (Low-level), which is called a third state (Tri-state). [0003] Please refer to figure 1 , figure 1 It is a schematic diagram of an existing pulse width modulation controller 1 . Such as figure 1 As shown, in the normal operation state, the pulse width modulation signal generator 10 controls the conduction or closure of the operation switch PMOS through the pulse width modulation signal PWMB,...

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Problems solved by technology

[0004] However, figure 1 The output of the buffer BF will be affected by the resistance-capacitance effect produced by the parasitic capacitance CPS in the driving circuit 12 and the external setting resistance RSET, therefore, as figure 2 As shown, the voltage level of the output signal Q of the existing PWM takes a period of time (for example, 180ns) before being pulled to a fixed third-state voltage level, resulting in poor switching performance.

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