Semiconductor memory device

Abstract

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions.The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects.The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

Description

[0001] [Related applications] [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2018-53939 (filing date: March 22, 2018). This application includes the entire content of the basic application by referring to this basic application. technical field [0003] Embodiments of the present invention generally relate to a semiconductor memory device. Background technique [0004] A semiconductor memory device in which memory cells are three-dimensionally arranged has been proposed. In such a semiconductor memory device, a laminate including a plurality of electrode layers is formed on a substrate, and a channel and a charge storage film are respectively formed in a plurality of memory holes penetrating the laminate. A contact is provided on the memory hole, and the channel and the bit line are connected through the contact. As the miniaturization of memory cells progresses, there is a problem that the intervals between...

AI Technical Summary

Problems solved by technology

With the development of miniaturization of memory cells, there is a problem that the interval of memory holes becomes smaller and it is difficult to form contacts

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