Ultra-wideband radio frequency front-end receiving circuit
A technology of radio frequency front-end and receiving circuit, which is applied in the field of ultra-wideband radio frequency front-end receiving circuit, and can solve problems such as difficult to achieve ultra-wideband and difficult to achieve full-band coverage of ultra-wideband
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Embodiment 1
[0060] See figure 1 , figure 1 It is a structural block diagram of an ultra-wideband radio frequency front-end receiving circuit provided by an embodiment of the present invention. As shown in the figure, an ultra-wideband radio frequency front-end receiving circuit of this embodiment includes an IQ phase-shifting circuit module 1 and a first radio frequency path module 2. The second radio frequency path module 3 and the path selection module 4, wherein, the IQ phase shifting circuit module 1 inputs the local oscillator differential signal LO, and the output ends are respectively connected to the first radio frequency path module 1 and the second radio frequency path module 2, the first radio frequency The channel module 2 inputs the first radio frequency signal RFIN_H, the second radio frequency channel module 2 inputs the second radio frequency signal RFIN_L, the output terminals of the first radio frequency channel module 1 and the second radio frequency channel module 2 ar...
Embodiment 2
[0065] This embodiment is a further description of the UWB RF front-end receiving circuit in Embodiment 1, please refer to figure 2 and image 3 , figure 2 It is a schematic structural diagram of an IQ phase-shifting circuit module provided by an embodiment of the present invention; image 3 It is a schematic structural diagram of an ultra-wideband radio frequency front-end receiving circuit provided by an embodiment of the present invention. As shown in the figure, the IQ phase shifting circuit module 1 includes a clock recovery unit 101, a first buffer Buffer1, a second buffer Buffer2, a first four-phase phase shifting unit 102 and a second four-phase phase shifting unit 103, wherein the clock The recovery unit 101 inputs the local oscillator differential signal LO for amplifying the local oscillator differential signal LO, and the output terminals are respectively connected to the first buffer Buffer1 and the second buffer Buffer2; the first buffer Buffer1 is connected ...
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