Long-delay instruction processing device, method, equipment and readable storage medium

Abstract

The invention discloses a long-delay instruction processing device, a long-delay instruction processing method and a computer readable storage medium. The long latency instruction is separated into afirst instruction for extracting a source operand and a source operator of the long latency instruction and a second instruction for reading an execution result of the first instruction and outputtingthe execution result to a register. A writing number and a reading number which are in one-to-one correspondence are generated for a first instruction and a second instruction through a numbering unit. Therefore, after an execution result of the first instruction is written into a buffer unit, the second instruction can read the corresponding execution result from the buffer unit. According to the long-delay instruction processing device and method, the long-delay instruction operation part and the result output part are separated. As a result, when the operation part is executed, a destination register for result output can be used by other instructions. The utilization rate of register resources is greatly increased.

Description

technical field [0001] The present invention relates to the field of computer instruction processing, in particular to a long-delay instruction processing device and method, instruction processing equipment and a computer-readable storage medium. Background technique [0002] The pursuit of performance is one of the themes of computer architecture design. For a software program, we often hope that it can run quickly to achieve the effect we want, and this is inseparable from the support of the underlying hardware. Usually, the compiler realizes the transition from software to hardware operation, and the program will be compiled into instructions one by one and handed over to the hardware for execution. [0003] Due to the advantages of fast register reading speed, most of the existing high-performance computer architectures adopt the load-store register architecture, that is, the input of an instruction needs to load data from the register, and the output result needs to sto...

AI Technical Summary

Problems solved by technology

[0013] One of the objectives of the present invention is to provide a long-delay instruction processing device to solve the problems of low performance of instruction processing equipment and waste of register resources caused by the long-time occupation of the corresponding register by the instruction during the operation of the long-delay instruction

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