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Formation method of three-dimensional memory

A memory, three-dimensional technology, applied in the direction of semiconductor devices, electric solid-state devices, electrical components, etc., can solve the problems of top layer selection gate tangent depression, affecting the performance of three-dimensional memory, etc., to reduce the number of mask layers and etching times, and reduce the process Cost, the effect of simplifying the process

Active Publication Date: 2020-09-11
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the process of etching the gate slit (GLS, gateline slit) used to form the common source of the array, it is easy to cause defects such as depressions in the tangent line of the top selection gate, which affects the performance of the three-dimensional memory

Method used

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  • Formation method of three-dimensional memory
  • Formation method of three-dimensional memory
  • Formation method of three-dimensional memory

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Embodiment Construction

[0037] The technical solution of the present invention will be further described in detail below in conjunction with the drawings and specific embodiments of the description. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0038] In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use inaccurate scales, which are only used to facilitate and clearly assis...

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Abstract

The embodiment of the present invention discloses a method for forming a three-dimensional memory, the forming method comprising: etching the stack structure along the first opening in the mask layer to form a first trench; while forming the first trench , etching the stacked structure along the second opening in the mask layer to form a second trench; wherein, the width of the top opening of the first trench is greater than the width of the top opening of the second trench, so The depth of the first groove is greater than the depth of the second groove.

Description

technical field [0001] Embodiments of the present invention relate to the field of integrated circuits, and in particular to a method for forming a three-dimensional memory. Background technique [0002] Usually, a top select gate tangent (TSG CUT, top select gatecut) is provided in the storage area of ​​the three-dimensional memory for dividing the top select gate (TSG, top select gate) of the storage area into two parts. After the tangent line of the top select gate is formed, there is also the formation of the common source of the array. During the process of etching the gate slit (GLS, gateline slit) used to form the common source of the array, it is easy to cause defects such as depressions in the tangent line of the top layer selection gate, which affects the performance of the three-dimensional memory. Contents of the invention [0003] In view of this, an embodiment of the present invention provides a method for forming a three-dimensional memory, including: [0...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157H01L27/11582
CPCH10B43/35H10B43/27
Inventor 姚兰薛磊
Owner YANGTZE MEMORY TECH CO LTD
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