31results about How to "Reduce the number of etch" patented technology

The invention discloses a process for Damascus, which can reduce the times of the development and etching in the process of forming grooves or inter-layered through holes on a substrate. The process comprises the following steps: (1) continuously carrying out exposure processing on a plurality of photoresist layers without development processing so as to form an exposure area; (2) carrying out the development processing on the exposure area so as to obtain a development area corresponding to the exposure area; and (3) etching a medium layer through the development area to form the required grooves or through holes. The process carries out the development and etching for one time on the exposure area obtained after multiple times of the exposure processing so as to obtain the required grooves or the through holes. Compared the prior art, the process centralizes to complete the development processing after each time of exposure processing at a time, thereby reducing the times of the development and etching and improving the efficiency.

The invention provides a three-dimensional nonvolatile memory array and a preparation method thereof, and belongs to the technical field of a nonvolatile memory in the manufacturing technology of super-large-scale integration. The three-dimensional nonvolatile memory array comprises a substrate and a bottom electrode / isolation medium stack structure; a deep groove is etched on the bottom electrode / isolation medium stack structure; a variable-resistance material and a top electrode layer are deposited on the side wall of the deep groove; the bottom electrode and the top electrode are crossed on the side wall of the deep groove; and a variable-resistance material is arranged between the cross points; each cross point forms a variable-resistance memory unit; all the variable-resistance memory units form a three-dimensional variable-resistance memory array; and the three-dimensional variable-resistance memories in the array are isolated by the isolation medium layer. The invention can improve the storage density of the variable-resistance memory, while simplifying the process and reducing the process cost.

The present invention provides a method for fabricating an integrated circuit device. The method includes providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and / or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region. The method can reduce a number of etching oxidation layers of an active region.

The invention discloses a preparation method for bandpass optical filters with the central wavelengths thereof gradually varied. According to the method, firstly, a first high-reflection film stack and spacing layers are prepared in a vacuum chamber through the plasma-enhanced chemical vapor deposition process according to the proportional relationship between the locations of the central wavelengths of bandpass optical filters and the optical thicknesses of the spacing layers. Secondly, different thickness etching means are conducted on the spacing layers at different locations in the vacuum chamber based on the combination of the ion-beam etching technique and the mask plate etching technique. In this way, the spacing layers corresponding to the locations of different central wavelengths are arranged in the form of ladder-like steps. Finally, a second high-reflection film stack is prepared through the plasma-enhanced chemical vapor deposition process, so that the bandpass optical filters with the central wavelengths thereof gradually varied are obtained. According to the technical scheme of the invention, based on the above preparation method for the bandpass optical filter with the central wavelength thereof gradually varied, n bandpass optical filters with the central wavelengths thereof gradually varied can be prepared each time through the preparation process of the first high-reflection film stack and the spacing layers, the ion beam and mask plate-combined etching process and the preparation process of the second high-reflection film stack. Therefore, the method is simple and high in efficiency.

The invention provides an MIM capacitor and a manufacturing method thereof. The manufacturing method comprises the steps of providing a semiconductor substrate, and forming a first metal layer on thesemiconductor substrate; forming an anti-reflection layer on the first metal layer; photoetching and etching the first metal layer and the anti-reflection layer to define an MIM capacitor region, wherein the first metal layer in the MIM capacitor region serves as a lower pole plate of the MIM capacitor, and the anti-reflection layer in the MIM capacitor region serves as a dielectric layer of the MIM capacitor; and forming an upper pole plate of the MIM capacitor on the anti-reflection layer in the MIM capacitor region. According to the manufacturing method provided by the invention, the anti-reflection layer reserved in the etched area is used as a dielectric layer of the capacitor at the same time, the etched area is continuously filled with metal to serve as the upper pole plate, an additional capacitor dielectric layer does not need to be manufactured, an additional photoetching process is not needed for defining the upper pole plate area any more, and the photoetching and etching frequency is reduced, so that the process cost is reduced, and the process period is shortened.

The invention provides a memory array structure, a preparation method thereof, a memory, a write-in method and a read-out method. The array structure comprises at least one memory cell which comprisesa superconducting device and a magnetic memory device which are overlapped and connected in series; at least one superconductive upper electrode which is arranged above the memory unit; at least onesuperconductive lower electrode arranged below the memory unit; at least one superconductive word line arranged above the memory unit or below the memory unit, wherein the superconductive word line isarranged close to the superconductive device in the memory unit. According to the invention, the magnetic memory device is organically combined with the superconducting integrated circuit, and the switching effect of the circuit is realized by using a superconducting device, thereby replacing a CMOS logic circuit. The memory array structure can achieve the operation of the memory at low temperature, guarantees that an MRAM achieves high-speed and high-density storage at a low working voltage, achieves the work based on different writing modes, forms an information reading mode suitable for the superconducting logic process, and is simple in structural design and beneficial to reduction of the etching frequency.

The invention discloses a forming method of layer capacitor, which uses an etch stop layer as capacitor medium without extra medium layer to deposit and form the capacitor medium, and form an upper metal connecting line and a capacitor upper pole plate by using the same metal layer. The method specifically comprises the following steps of: depositing the etch stop layer and an inter-level dielectrics film after a capacitor lower pole plate is formed; a capacitor plate groove is formed in the inter-level dielectrics firm by etching, wherein, the capacitor plate groove passes the inter-level dielectrics film and stops at the etch stop layer and part of the etch stop layer is exposed, and further the exposed etch stop layer is used as the capacitor medium; and forming the capacitor upper pole plate in the capacitor plate groove. Compared with the prior art, the invention reduces times for depositing and etching and simplifies the process flow.

The invention provides a manufacturing method of a backlight module. The manufacturing method comprises the steps: forming a first conducting layer and a first insulating layer on a substrate; formingan active material layer on the first insulating layer; patterning the first insulating layer and the active material layer by using a multi-section mask plate so as to expose part of the first conducting layer and enable the active material layer to form an active member; and forming a third conducting layer on the active member to form a source electrode and a drain electrode of the backlight module. According to the invention, the openings of the active member and the first electrode of the binding terminal of the flexible circuit board are simultaneously formed by using the multi-sectionmask plate, so that the third conducting layer can simultaneously form the source and drain electrodes, the second electrode of the binding terminal of the flexible circuit board and the binding end of the light-emitting element, the etching frequency of a manufacturing process is reduced, the process difficulty of the backlight module is simplified, and the process efficiency is improved.

The embodiment of the present invention discloses a three-dimensional memory, including: a substrate, and a stacked structure on the substrate; the stacked structure includes several gate layers, and the several gate layers are arranged along the The direction is stacked at intervals; the stacked structure has a step area, and the lower step in the step area protrudes from the upper step along the direction parallel to the substrate; at least one step in the step area includes two gate layers, the One of the two gate layers is connected to the first sub-conductive plug, and the other gate layer is connected to the second sub-conductive plug. In addition, the embodiment of the invention also discloses a method for preparing a three-dimensional memory.

The embodiment of the invention provides a forming method of a three-dimensional phase change memory and the three-dimensional phase change memory, and the method comprises the steps: employing a plurality of initial etching patterns which extend along a first direction, and etching a first mask lamination layer, so as to form a first etching mask lamination layer; forming a second mask lamination layer on the surface of the first etching mask lamination layer; a plurality of secondary etching patterns extending in the second direction are adopted, the second mask lamination layer and the first etching mask lamination layer are etched in sequence, a secondary etching mask lamination layer is formed, and the secondary etching mask lamination layer is provided with latticed patterns; and etching the phase change storage unit lamination layer by taking the secondary etching mask lamination layer as a mask so as to form a columnar phase change storage unit.

The invention provides a monolithic integration method of a hyperspectral image sensor, comprising: forming a bottom reflection layer on the surface of the photosensitive area of ​​a CMOS image sensor wafer; adopting multiple thin film deposition processes and multiple photolithography and etching processes A plurality of stepped structures are formed on the bottom reflective layer to form a transparent cavity layer; a thin film is deposited on the transparent cavity layer to form a top reflective layer. The monolithic integration method of the hyperspectral image sensor provided by the present invention realizes the precise control of the thickness of each step of the transparent cavity layer by controlling the thin film deposition process conditions, and optimizes the accumulation of inhomogeneity caused by the etching process in the prior art The problem. The invention also provides a hyperspectral image sensor and an imaging device containing the hyperspectral image sensor.

The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method thereof. The forming method of the three-dimensional memory includes the following steps: providing a substrate with a stacked layer on the substrate, the stacked layer including a core area and a stepped area located at the periphery of the core area; The stepped area; forming a plurality of sub-regions arranged along the first direction in the partitioned stepped structure region, each of the sub-regions includes a plurality of sub-structures arranged in a step-like manner along the first direction, and each of the The substructures are multi-level ladders arranged along the second direction, and the heights of the steps in any two sub-regions are different. The invention simplifies the manufacturing process of the three-dimensional memory, reduces the manufacturing cost of the three-dimensional memory, and simultaneously realizes the improvement of the performance of the three-dimensional memory.

The invention discloses a process for Damascus, which can reduce the times of the development and etching in the process of forming grooves or inter-layered through holes on a substrate. The process comprises the following steps: (1) continuously carrying out exposure processing on a plurality of photoresist layers without development processing so as to form an exposure area; (2) carrying out the development processing on the exposure area so as to obtain a development area corresponding to the exposure area; and (3) etching a medium layer through the development area to form the required grooves or through holes. The process carries out the development and etching for one time on the exposure area obtained after multiple times of the exposure processing so as to obtain the required grooves or the through holes. Compared the prior art, the process centralizes to complete the development processing after each time of exposure processing at a time, thereby reducing the times of the development and etching and improving the efficiency.

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a three-dimensional memory and a method for forming the same. The method for forming the three-dimensional memory includes the following steps: providing a substrate with a stack layer on the substrate, the stack layer including a core region and a stepped region distributed around the periphery of the core region; forming a plurality of partitioned stepped structure regions in the stepped area; a plurality of sub-partition structures arranged along a first direction are formed in the sub-division stepped structure area, and the heights of the plurality of the sub-partition structures are gradually changed along the first direction, and the first direction is the The stepped area points in the direction of the core area. The invention can reduce the number of masks and the times of etching, thereby simplifying the manufacturing process of the three-dimensional memory and reducing the manufacturing cost of the three-dimensional memory.

The invention provides a memory array structure, a preparation method thereof, a memory, a write-in method and a read-out method. The array structure comprises at least one memory cell which comprisesa superconducting device and a magnetic memory device which are overlapped and connected in series; at least one superconductive upper electrode which is arranged above the memory unit; at least onesuperconductive lower electrode arranged below the memory unit; at least one superconductive word line arranged above the memory unit or below the memory unit, wherein the superconductive word line isarranged close to the superconductive device in the memory unit. According to the invention, the magnetic memory device is organically combined with the superconducting integrated circuit, and the switching effect of the circuit is realized by using a superconducting device, thereby replacing a CMOS logic circuit. The memory array structure can achieve the operation of the memory at low temperature, guarantees that an MRAM achieves high-speed and high-density storage at a low working voltage, achieves the work based on different writing modes, forms an information reading mode suitable for the superconducting logic process, and is simple in structural design and beneficial to reduction of the etching frequency.

The present invention provides a MIM capacitor and a manufacturing method thereof, the manufacturing method comprising: providing a semiconductor substrate, forming a first metal layer on the semiconductor substrate; forming an anti-reflection layer on the first metal layer; Engraving and etching the first metal layer and the anti-reflection layer to define a MIM capacitor area, the first metal layer in the MIM capacitor area serves as the lower plate of the MIM capacitor, and in the MIM capacitor area The anti-reflection layer is used as the dielectric layer of the MIM capacitor; the upper plate of the MIM capacitor is formed on the anti-reflection layer in the region of the MIM capacitor. In the manufacturing method of the present invention, the anti-reflection layer retained in the etched area is used as the dielectric layer of the capacitor at the same time, and the metal is continued to be filled in the etched area as the upper plate, and no additional dielectric layer of the capacitor is required. , and no additional photolithography process is required to define the upper plate area, reducing the number of photolithography and etching, thereby reducing the process cost and shortening the process cycle.

The invention discloses a forming method of layer capacitor, which uses an etch stop layer as capacitor medium without extra medium layer to deposit and form the capacitor medium, and form an upper metal connecting line and a capacitor upper pole plate by using the same metal layer. The method specifically comprises the following steps of: depositing the etch stop layer and an inter-level dielectrics film after a capacitor lower pole plate is formed; a capacitor plate groove is formed in the inter-level dielectrics firm by etching, wherein, the capacitor plate groove passes the inter-level dielectrics film and stops at the etch stop layer and part of the etch stop layer is exposed, and further the exposed etch stop layer is used as the capacitor medium; and forming the capacitor upper pole plate in the capacitor plate groove. Compared with the prior art, the invention reduces times for depositing and etching and simplifies the process flow.

The invention discloses a preparation method of a SiC high-voltage power device junction terminal. Firstly, according to blocking voltage requirement of different levels, a number (2n) of steps is determined and the mask pattern structure design is carried out; then a multi-level step structure is formed on a SiC sample through multiple times of step preparation process (including preparing a hardmask layer, etching a step region, and removing a silicon oxide hard mask layer), and finally steps of 2n levels are formed through (n+1) times of step etching. For making the SiC high-voltage powerdevice junction terminal with the steps of multiple levels, the terminal can be prepared only with very few times of step etching, thus while the steps of multiple levels can be realized and SiC high-voltage power device blocking voltage is greatly raised, the preparation process of the multi-step junction terminal can be greatly simplified, and thus the method has a great application prospect inthe SiC high-voltage power device.

The embodiment of the present invention discloses a method for forming a three-dimensional memory, the forming method comprising: etching the stack structure along the first opening in the mask layer to form a first trench; while forming the first trench , etching the stacked structure along the second opening in the mask layer to form a second trench; wherein, the width of the top opening of the first trench is greater than the width of the top opening of the second trench, so The depth of the first groove is greater than the depth of the second groove.