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Integrating method for multiple metal gates

An integrated method and metal gate technology, applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., can solve the problems of reducing device reliability, increasing thermal budget, poor alloy uniformity and controllability, etc., to reduce etching The number of times, improve the uniformity and controllability, reduce the effect of etching damage

Inactive Publication Date: 2015-12-30
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The multilayer metal alloy annealing process in this method adds additional thermal budget and reduces device reliability; in addition, the uniformity and controllability of the alloy is also poor

Method used

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  • Integrating method for multiple metal gates
  • Integrating method for multiple metal gates
  • Integrating method for multiple metal gates

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] According to the following steps, three thresholds (Vt1, Vt2, Vt3 can be achieved; the specific values ​​are based on the requirements of different technology generations and the performance of different types of devices (such as high-performance logic devices, low-power logic devices, I / O devices, etc.) Bulk silicon planar device for setup:

[0043] 1) Processed on a (100) bulk silicon substrate according to a standard bulk silicon plane process until the source / drain impurities are activated, such as figure 2 shown;

[0044] 2) PECVDSiO 2 as an isolation layer;

[0045] 3) CMPSiO 2 until the top of the false grid is exposed;

[0046] 4) Isotropic etching to remove false gates, such as image 3 shown;

[0047] 5) ALD1.5nmHfO2 is used as insulating gate dielectric;

[0048] 6) ALD5nmTaN as buffer layer, such as Figure 4 shown;

[0049] 7) The gate lines of the photolithographic device 1 (eg, having a threshold value Vt1) (the photoresist at the gate lines is ...

Embodiment 2

[0057] On the basis of Example 1, the following adjustments can be made to realize bulk silicon FinFET devices with three thresholds:

[0058] 1) In step 1 of Embodiment 1, the (100) bulk silicon substrate is processed according to the standard bulk silicon FinFET process until the source / drain impurities are activated;

[0059]2) In Step 5 of Embodiment 1, the type and thickness of the HK medium can be optimized and adjusted according to the actual technical node requirements;

[0060] 3) In steps 8 and 10 of embodiment 1, the type and thickness of metal 1, metal 2, and metal 3 can be optimized and adjusted according to the actual technical node requirements;

[0061] 4) In Step 11 of Embodiment 1, the type and thickness of the metal M can be optimized and adjusted according to the actual technical node requirements;

[0062] 5) In Step 13 of Embodiment 1, device integration is subsequently completed according to the standard bulk silicon FinFET back-end process.

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Abstract

The invention discloses an integrating method for multiple metal gates, and belongs to the technical field of super-large-scale integrated circuit manufacturing. The integrating method for the multiple metal gates is achieved on the basis of successive stripping of an undergate technology by adopting a stripping technology. Compared with a depositing-annealing alloy method of Takashi Matsukawa and the like, the method has the advantages that no additional heat budget exists, the uniformity and controllability of the technology are improved, etching damage is reduced, the technological difficulty is reduced, and the material selection range is widened.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing, and relates to a method for realizing the integration of various metal gates through successive stripping. Background technique [0002] As the feature size of semiconductor devices shrinks, in order to more effectively suppress the short channel effect and improve the driving capability, the equivalent electrical thickness (Equivalent Electrical Thickness, EOT) of the gate dielectric of the device continues to decrease; however, conventional dielectrics (such as SiO2, SiON, etc.) are mainly EOT is reduced by reducing the physical thickness of the dielectric, thus causing an increase in gate leakage current. In order to suppress the gate leakage current and improve the driving capability (ie, reduce the EOT of the dielectric without significantly reducing the physical thickness of the dielectric), it is necessary to use a high-kdielectric (HK dielectric)...

Claims

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Application Information

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IPC IPC(8): H01L21/8234
CPCH01L21/823437H01L21/823431H01L21/82345
Inventor 黎明杨远程陈珙樊捷闻张昊黄如
Owner PEKING UNIV
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