Array substrate manufacturing method and array substrate

Abstract

The invention provides an array substrate manufacturing method and an array substrate. The array substrate manufacturing method comprises the steps: sequentially depositing a grid electrode, a grid electrode insulating layer, a metal oxide semiconductor layer and a source and drain metal layer on a substrate, enabling an impedance value per square of a metal material of the source and drain metallayer to be lower than 0.08 ohm / m<2>, and enabling the thickness of the source and drain metal layer to be 100nm-300nm; forming a first photoresist pattern on the source and drain metal layer; carrying out primary wet etching on the metal oxide semiconductor layer and the source and drain metal layer; performing primary ashing processing on the first photoresist pattern to form a second photoresist pattern; and performing primary dry etching on the patterned source and drain metal layer to form a channel. According to the manufacturing method of the array substrate and the array substrate provided by the invention, a risks of a parasitic capacitance and the like of a product can be reduced.

Description

technical field [0001] The invention relates to the technical field of liquid crystal display, in particular to a method for manufacturing an array substrate and the array substrate. Background technique [0002] With the development of display technology, display panels are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, and notebook computers, and become the mainstream of display devices. In order to realize high-resolution display, as a main driving element in a display panel, the size of a thin film transistor (Thin Film Transistor, TFT for short) device needs to be "miniaturized". Realizing a Back Channel Etching (BCE) structure is the key to "miniaturization" of the TFT device size. [0003] In the existing manufacturing process of the array substrate using back channel etching, the source and drain metal layers are deposited on the metal oxide semiconductor layer, and the source and drain metal laye...

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Problems solved by technology

[0005] Embodiments of the present invention provide a method for manufacturing an array substrate and an array substrate, which are used to solve the problem of performing different times of wet etching on the metal oxide semiconductor layer and the source-drain metal layer in the existing patterning process. Lead to severe tailing of the metal oxide semiconductor layer, which in turn leads to increased risks such as product parasitic capacitance

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