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A kind of three-dimensional memory and its preparation method

A memory, three-dimensional technology, applied in semiconductor devices, electric solid-state devices, electrical components, etc., can solve the problems of increasing the cost of three-dimensional memory technology, reduce exposure and etching times, reduce process costs, and ensure good contact.

Active Publication Date: 2020-06-09
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The etching of the step area is generally realized through the process of multiple exposure-dry etching-etching advancement, and each gate layer corresponds to a step; however, due to the increasing number of stacked layers, the corresponding exposure and etching times increase with time. This will undoubtedly greatly increase the process cost of 3D memory and bring greater challenges to process stability.

Method used

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  • A kind of three-dimensional memory and its preparation method
  • A kind of three-dimensional memory and its preparation method
  • A kind of three-dimensional memory and its preparation method

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preparation example Construction

[0067] The embodiment of the present invention also provides a method for preparing a three-dimensional memory; for details, please refer to the attached image 3 . As shown, the method includes the following steps:

[0068] Step 101, providing a substrate and a stacked structure on the substrate, the stacked structure includes a plurality of gate layers, and the plurality of gate layers are stacked at intervals along a direction perpendicular to the substrate; in the stacked structure There is a step area, the lower step in the step area protrudes from the upper step along the direction parallel to the substrate, and at least one step in the step area includes two gate layers;

[0069] Step 102, forming a conductive plug on the step region, one gate layer of the two gate layers is connected to the first sub-conductive plug of the conductive plug, and the other gate layer is connected to the first sub-conductive plug of the conductive plug. The second sub-conductive plug in ...

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Abstract

The embodiment of the present invention discloses a three-dimensional memory, including: a substrate, and a stacked structure on the substrate; the stacked structure includes several gate layers, and the several gate layers are arranged along the The direction is stacked at intervals; the stacked structure has a step area, and the lower step in the step area protrudes from the upper step along the direction parallel to the substrate; at least one step in the step area includes two gate layers, the One of the two gate layers is connected to the first sub-conductive plug, and the other gate layer is connected to the second sub-conductive plug. In addition, the embodiment of the invention also discloses a method for preparing a three-dimensional memory.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a preparation method thereof. Background technique [0002] Three-dimensional NAND memory is the mainstream structure of non-volatile memory at present, and its core storage structure is composed of storage area and step area (Stair Steps area, SS area). Among them, a number of channel holes (ChannelHole, CH) are set in the storage area for storing information; the step area is set around the storage area, and is used to transmit control information to the storage area, so as to realize information storage in the storage area. reading and writing. A contact hole is generally provided on the gate layer of the stepped area, and a conductive plug is formed by filling the contact hole with a conductive material. One end of the conductive plug is connected to the gate layer, and the other end is connected to the subsequent interconnection line. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L27/11548H01L27/11556H01L27/11575H01L27/11582H10B69/00H10B41/27H10B41/50H10B43/27H10B43/50
CPCH10B69/00H10B41/50H10B41/27H10B43/50H10B43/27
Inventor 王启光
Owner YANGTZE MEMORY TECH CO LTD
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