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Process for Damascus

A process method and substrate technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of complex processing and low efficiency, and achieve the effect of improving efficiency and reducing the number of times of development and etching

Active Publication Date: 2011-03-23
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] It can be seen that the traditional double damascene process requires at least two developments and etchings, which makes the processing process more complicated and inefficient. How to improve the process, reduce the number of developments and etchings, simplify the processing process and improve efficiency is an important issue in this field. topic

Method used

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  • Process for Damascus
  • Process for Damascus
  • Process for Damascus

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Embodiment Construction

[0022] In order to make the purpose and features of the present invention more comprehensible, the specific implementation manners of the present invention will be further described below in conjunction with the accompanying drawings.

[0023] The damascene process method of the present invention can reduce the number of times of development and etching during the formation of the groove on the substrate (or the interlayer via hole on a dielectric layer), and it includes the following steps:

[0024] Continuously performing exposure treatment on a plurality of photoresist layers without developing treatment in between, thereby forming an exposure area;

[0025] performing a developing treatment on the exposed area to obtain a developed area corresponding to the exposed area;

[0026] The base or a dielectric layer is etched through the above-mentioned developing area to form the desired groove or through hole.

[0027] In order to better understand the present invention, the ...

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Abstract

The invention discloses a process for Damascus, which can reduce the times of the development and etching in the process of forming grooves or inter-layered through holes on a substrate. The process comprises the following steps: (1) continuously carrying out exposure processing on a plurality of photoresist layers without development processing so as to form an exposure area; (2) carrying out the development processing on the exposure area so as to obtain a development area corresponding to the exposure area; and (3) etching a medium layer through the development area to form the required grooves or through holes. The process carries out the development and etching for one time on the exposure area obtained after multiple times of the exposure processing so as to obtain the required grooves or the through holes. Compared the prior art, the process centralizes to complete the development processing after each time of exposure processing at a time, thereby reducing the times of the development and etching and improving the efficiency.

Description

technical field [0001] The invention relates to a damascene process method, in particular to a method for reducing the number of development and etching times in the damascene process. Background technique [0002] The traditional double damascene process requires at least two development and etching, the following combination figure 1 Briefly describe the two development and etching processes in the traditional double damascene process. As shown in the picture, [0003] First, perform the first development and etching, namely steps (1) to (3), as follows: [0004] Step (1), the first exposure: forming a photoresist layer 12 on the substrate 10, and then exposing it to form the required exposure area 14; [0005] Step (2), the first development: remove the photoresist in the exposure area 14 by chemical treatment; [0006] Step (3), first etching: under the protection of the remaining photoresist, the substrate 10 is etched for the first time and the remaining photoresis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/308H01L21/768H01L21/311
Inventor 王金丽
Owner SEMICON MFG INT (SHANGHAI) CORP
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