A Cache Side Channel Attack Defense Method Based on Local Random Mapping

Abstract

The invention discloses a cache side channel attack defense method based on local random mapping. The method comprises: (1) constructing a system composed of a CPU, a first-level cache, a second-levelcache, an ultimate cache, a storage controller and a memory; (2) calculating and generating n alternative cache groups for each physical address; (3) when cache access occurs, calculating n alternative cache group indexes corresponding to n alternative cache groups according to a physical address, storing the n alternative cache group indexes in n index registers, and searching the n cache groupsin parallel to determine whether cache hit or cache loss occurs; when the cache is lost, randomly selecting one of the n alternative cache groups as a target cache group to which the cache is finallymapped; and (5) in the target cache group, if the record with the valid bit of 0 exists, writing the memory block taken from the memory into the target cache group, otherwise, selecting one record toreplace one existing memory block. The method has the advantages of high safety, high speed, friendly final cache and the like which are not possessed by the existing method.

Description

technical field [0001] The invention belongs to the field of cache security, in particular to a cache side channel attack defense method based on local random mapping. Background technique [0002] A cache timing attack can cause severe information disclosure by exploiting the difference in latency between a cache hit and a cache miss in memory access. Although the memory spaces of different processes are isolated from each other for security reasons, the cache is still shared by different processes. Thus, a cache access by one process may affect the hit or miss of another process accessing the cache. Since the access delay caused by a cache hit and a cache miss is significantly different, the cache hit or miss can be effectively known by measuring the access delay. Thus, an attacker process can infer a victim process's cache access by measuring its own cache access latency. This means can be used in two attack methods, side channel attack (side channel attack) and covert...

AI Technical Summary

Problems solved by technology

[0006] However, in the existing literature, no practical defense scheme against cache timing attacks has been proposed

Most of the existing defense schemes have obvious defects: sacrificing the normal function of the system or not being able to completely defend against cache timing attacks

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