Semiconductor Package and Method For Forming Same

Abstract

The embodiment of the invention provides a semiconductor package and a method for forming the same. The method includes the steps: placing a package component over a carrier, encapsulating the packagecomponent in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via. The embodiment of the invention also provides a package.

Description

Technical field [0001] The present invention relates to the field of semiconductors, and more particularly, to semiconductor packages and methods of forming them. Background technique [0002] With the development of semiconductor technology, semiconductor chips / dies become smaller and smaller. At the same time, more functions need to be integrated into the semiconductor die. Therefore, semiconductor dies need to pack more and more I / O pads into a smaller area, and the density of I / O pads increases rapidly over time. Therefore, the packaging of the semiconductor die becomes more difficult, which adversely affects the yield of the package. [0003] Traditional packaging technologies can be divided into two categories. In the first category, the die on the wafer is packaged before sawing. This packaging technology has some advantageous features, such as higher yield and lower cost. In addition, less underfill or molding compound is required. However, this packaging technology a...

AI Technical Summary

Problems solved by technology

Due to the limited area of ​​the die, the number of I / O pads is limited due to the limitation of the pitch of the I / O pads

If the pitch of the pads is to be reduced, solder bridging may occur

Additionally, with a fixed ball size requirement, the solder balls must be of a certain size, which in turn limits the number of solder balls that can be packaged on the die surface

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